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| H A D | gic_v2.cc | 13337:36a857f9adaf Thu Oct 11 18:42:00 EDT 2018 Adrien Pesle <adrien.pesle@arm.com> dev-arm: Don't panic when EOIR a non active PPI GIC architecture specification says that writing EOIR with a not active irq it is an unpredictable behavior. So, just warn when it happens for a PPI case, like it is already done in SPI case. Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13556 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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