Searched hist:13 (Results 276 - 300 of 1864) sorted by relevance
| /gem5/src/arch/sparc/ | ||
| H A D | handlers.hh | 4989:3e9d532cf998 Mon Aug 13 19:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault ASI accesses work. |
| /gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/ | ||
| H A D | endian_conversion.py | 6478:2ec6bfc8f9c7 Fri Aug 07 13:12:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the qaud width bswap instruction handle the fact that 32 bit operations zero extend. |
| H A D | translate.py | 5927:5e3367b103da Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Do a merge for the zero extension microop. |
| /gem5/src/arch/x86/ | ||
| H A D | stacktrace.hh | 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help |
| /gem5/util/ | ||
| H A D | checkpoint_aggregator.py | 7443:cbedf338fc44 Thu Jun 03 13:34:00 EDT 2010 Lisa Hsu <Lisa.Hsu@amd.com> utils: checkpoint aggregator: some physmem files are too big to read at once, break it up into reading one page at a time. Also, avoid redoing a aggregating a checkpoint that's already done. |
| /gem5/src/arch/null/ | ||
| H A D | cpu_dummy.hh | 9850:87d6b41749e9 Wed Sep 04 13:22:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> arch: Resurrect the NOISA build target and rename it NULL This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. |
| /gem5/tests/quick/se/70.tgen/ | ||
| H A D | tgen-simple-mem.trc | 9402:f6e3c60f04e5 Mon Jan 07 13:05:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> cpu: Add support for protobuf input for the trace generator This patch adds support for reading input traces encoded using protobuf according to what is done in the CommMonitor. A follow-up patch adds a Python script that can be used to convert the previously used ASCII traces to protobuf equivalents. The appropriate regression input is updated as part of this patch. |
| /gem5/src/arch/arm/freebsd/ | ||
| H A D | freebsd.cc | 11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct The structure definition only had the open system call flag set in mind when it was named, so we rename it here with the intention of using it to define additional tables to translate flags for other system calls in the future. |
| /gem5/src/arch/arm/linux/ | ||
| H A D | linux.cc | 11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps For O3, which has a stat that counts reg reads, there is an additional reg read per mmap() call since there's an arg we no longer ignore. Otherwise, stats should not be affected. 11382:654272b82e94 Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: add many Linux kernel flags 11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct The structure definition only had the open system call flag set in mind when it was named, so we rename it here with the intention of using it to define additional tables to translate flags for other system calls in the future. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
| /gem5/src/arch/x86/linux/ | ||
| H A D | linux.cc | 11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps For O3, which has a stat that counts reg reads, there is an additional reg read per mmap() call since there's an arg we no longer ignore. Otherwise, stats should not be affected. 11382:654272b82e94 Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: add many Linux kernel flags 11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct The structure definition only had the open system call flag set in mind when it was named, so we rename it here with the intention of using it to define additional tables to translate flags for other system calls in the future. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
| /gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/ | ||
| H A D | simerr | 11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change. SE O3 runs see an additional reg read per mmap() call. |
| /gem5/tests/quick/se/00.hello/ref/mips/linux/simple-timing/ | ||
| H A D | simerr | 11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries. |
| /gem5/configs/ruby/ | ||
| H A D | __init__.py | 11670:6ce719503eae Thu Oct 13 03:17:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> ruby: Fix regressions and make Ruby configs Python packages This patch moves the addition of network options into the Ruby module to avoid the regressions all having to add it explicitly. Doing this exposes an issue in our current config system though, namely the fact that addtoPath is relative to the Python script being executed. Since both example and regression scripts use the Ruby module we would end up with two different (relative) paths being added. Instead we take a first step at turning the config modules into Python packages, simply by adding a __init__.py in the configs/ruby, configs/topologies and configs/network subdirectories. As a result, we can now add the top-level configs directory to the Python search path, and then use the package names in the various modules. The example scripts are also updated, and the messy path-deducing variations in the scripts are unified. |
| /gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/ | ||
| H A D | simout | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references |
| /gem5/src/arch/mips/ | ||
| H A D | idle_event.cc | 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode |
| /gem5/src/arch/power/ | ||
| H A D | isa.cc | 9384:877293183bdf Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@arm.com> arch: Make the ISA class inherit from SimObject The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU. |
| /gem5/src/arch/x86/insts/ | ||
| H A D | microfpop.cc | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
| /gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/ | ||
| H A D | stats.txt | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references |
| /gem5/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/ | ||
| H A D | simout | 11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries. 11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change. SE O3 runs see an additional reg read per mmap() call. 11156:a37dda0f0202 Mon Oct 05 14:13:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update SMT tests to correctly configure CPUs The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup the number of threads before creating interrupt controllers, which confused the constructor in BaseCPU. This changeset adds SMT support to the test configuration infrastructure. |
| /gem5/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/ | ||
| H A D | config.ini | 12137:d877205ec1bc Thu Jul 13 18:00:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> tests: Upate RISC-V binaries and results This patch updates the binaries and results for hello and insttest regressions using the compressed extension. Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e Reviewed-on: https://gem5-review.googlesource.com/4042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | config.json | 12137:d877205ec1bc Thu Jul 13 18:00:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> tests: Upate RISC-V binaries and results This patch updates the binaries and results for hello and insttest regressions using the compressed extension. Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e Reviewed-on: https://gem5-review.googlesource.com/4042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | simout | 12137:d877205ec1bc Thu Jul 13 18:00:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> tests: Upate RISC-V binaries and results This patch updates the binaries and results for hello and insttest regressions using the compressed extension. Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e Reviewed-on: https://gem5-review.googlesource.com/4042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/ | ||
| H A D | config.ini | 12137:d877205ec1bc Thu Jul 13 18:00:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> tests: Upate RISC-V binaries and results This patch updates the binaries and results for hello and insttest regressions using the compressed extension. Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e Reviewed-on: https://gem5-review.googlesource.com/4042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| H A D | config.json | 12137:d877205ec1bc Thu Jul 13 18:00:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> tests: Upate RISC-V binaries and results This patch updates the binaries and results for hello and insttest regressions using the compressed extension. Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e Reviewed-on: https://gem5-review.googlesource.com/4042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/ | ||
| H A D | config.ini | 12137:d877205ec1bc Thu Jul 13 18:00:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> tests: Upate RISC-V binaries and results This patch updates the binaries and results for hello and insttest regressions using the compressed extension. Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e Reviewed-on: https://gem5-review.googlesource.com/4042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
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