111308Santhony.gutierrez@amd.com 211308Santhony.gutierrez@amd.com---------- Begin Simulation Statistics ---------- 311308Santhony.gutierrez@amd.comsim_seconds 0.000014 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 13821 # Number of ticks simulated 511680SCurtis.Dunham@arm.comfinal_tick 13821 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611308Santhony.gutierrez@amd.comsim_freq 1000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_tick_rate 253620 # Simulator tick rate (ticks/s) 811860Sandreas.hansson@arm.comhost_mem_usage 491252 # Number of bytes of host memory used 911860Sandreas.hansson@arm.comhost_seconds 0.05 # Real time elapsed on the host 1011308Santhony.gutierrez@amd.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1111308Santhony.gutierrez@amd.comsystem.clk_domain.clock 1 # Clock period in ticks 1211680SCurtis.Dunham@arm.comsystem.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 1311680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytes_read::dir_cntrl0 16384 # Number of bytes read from this memory 1411680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytes_read::total 16384 # Number of bytes read from this memory 1511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytes_written::dir_cntrl0 896 # Number of bytes written to this memory 1611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytes_written::total 896 # Number of bytes written to this memory 1711680SCurtis.Dunham@arm.comsystem.mem_ctrls.num_reads::dir_cntrl0 256 # Number of read requests responded to by this memory 1811680SCurtis.Dunham@arm.comsystem.mem_ctrls.num_reads::total 256 # Number of read requests responded to by this memory 1911680SCurtis.Dunham@arm.comsystem.mem_ctrls.num_writes::dir_cntrl0 14 # Number of write requests responded to by this memory 2011680SCurtis.Dunham@arm.comsystem.mem_ctrls.num_writes::total 14 # Number of write requests responded to by this memory 2111680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_read::dir_cntrl0 1185442443 # Total read bandwidth from this memory (bytes/s) 2211680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_read::total 1185442443 # Total read bandwidth from this memory (bytes/s) 2311680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_write::dir_cntrl0 64828884 # Write bandwidth from this memory (bytes/s) 2411680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_write::total 64828884 # Write bandwidth from this memory (bytes/s) 2511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_total::dir_cntrl0 1250271326 # Total bandwidth to/from this memory (bytes/s) 2611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_total::total 1250271326 # Total bandwidth to/from this memory (bytes/s) 2711680SCurtis.Dunham@arm.comsystem.mem_ctrls.readReqs 256 # Number of read requests accepted 2811680SCurtis.Dunham@arm.comsystem.mem_ctrls.writeReqs 14 # Number of write requests accepted 2911680SCurtis.Dunham@arm.comsystem.mem_ctrls.readBursts 256 # Number of DRAM read bursts, including those serviced by the write queue 3011680SCurtis.Dunham@arm.comsystem.mem_ctrls.writeBursts 14 # Number of DRAM write bursts, including those merged in the write queue 3111680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesReadDRAM 15488 # Total number of bytes read from DRAM 3211680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesReadWrQ 896 # Total number of bytes read from write queue 3311308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM 3411680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesReadSys 16384 # Total read bytes from the system interface side 3511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesWrittenSys 896 # Total written bytes from the system interface side 3611680SCurtis.Dunham@arm.comsystem.mem_ctrls.servicedByWrQ 14 # Number of DRAM read bursts serviced by the write queue 3711308Santhony.gutierrez@amd.comsystem.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 3811308Santhony.gutierrez@amd.comsystem.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 3911680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::0 99 # Per bank write bursts 4011680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::1 69 # Per bank write bursts 4111680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::2 62 # Per bank write bursts 4211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts 4311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts 4411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts 4511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts 4611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts 4711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts 4811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts 4911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts 5011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts 5111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts 5211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts 5311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts 5411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts 5511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts 5611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts 5711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts 5811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts 5911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts 6011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts 6111308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts 6211308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts 6311308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 6411308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts 6511308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts 6611308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts 6711308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts 6811308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts 6911308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts 7011308Santhony.gutierrez@amd.comsystem.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts 7111308Santhony.gutierrez@amd.comsystem.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 7211308Santhony.gutierrez@amd.comsystem.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 7311680SCurtis.Dunham@arm.comsystem.mem_ctrls.totGap 13710 # Total gap between requests 7411308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 7511308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 7611308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 7711308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 7811308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 7911308Santhony.gutierrez@amd.comsystem.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 8011680SCurtis.Dunham@arm.comsystem.mem_ctrls.readPktSize::6 256 # Read request sizes (log2) 8111308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 8211308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 8311308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 8411308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 8511308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 8611308Santhony.gutierrez@amd.comsystem.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 8711680SCurtis.Dunham@arm.comsystem.mem_ctrls.writePktSize::6 14 # Write request sizes (log2) 8811680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdQLenPdf::0 199 # What read queue length does an incoming req see 8911680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdQLenPdf::1 36 # What read queue length does an incoming req see 9011680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdQLenPdf::2 6 # What read queue length does an incoming req see 9111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see 9211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 9311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 9411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 9511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 9611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 9711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 9811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 9911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 10011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 10111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 10211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 10311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 10411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 10511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 10611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 10711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 10811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 10911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 11011308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 11111308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 11211308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 11311308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 11411308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 11511308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 11611308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 11711308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 11811308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 11911308Santhony.gutierrez@amd.comsystem.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 12011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 12111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 12211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 12311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 12411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 12511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 12611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 12711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 12811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 12911680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 13011680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 13111680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 13211680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 13311680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 13411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see 13511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see 13611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see 13711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see 13811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see 13911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see 14011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see 14111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see 14211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see 14311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see 14411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see 14511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see 14611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see 14711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see 14811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see 14911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see 15011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see 15111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see 15211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see 15311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 15411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 15511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 15611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 15711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 15811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 15911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 16011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 16111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 16211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 16311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 16411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 16511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 16611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 16711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 16811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 16911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 17011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 17111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 17211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 17311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 17411308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 17511308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 17611308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 17711308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 17811308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 17911308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 18011308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 18111308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 18211308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 18311308Santhony.gutierrez@amd.comsystem.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 18411308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::samples 15 # Bytes accessed per row activation 18511308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::mean 913.066667 # Bytes accessed per row activation 18611308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::gmean 883.543279 # Bytes accessed per row activation 18711308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::stdev 210.139908 # Bytes accessed per row activation 18811308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::512-639 3 20.00% 20.00% # Bytes accessed per row activation 18911308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::896-1023 1 6.67% 26.67% # Bytes accessed per row activation 19011308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::1024-1151 11 73.33% 100.00% # Bytes accessed per row activation 19111308Santhony.gutierrez@amd.comsystem.mem_ctrls.bytesPerActivate::total 15 # Bytes accessed per row activation 19211680SCurtis.Dunham@arm.comsystem.mem_ctrls.totQLat 2184 # Total ticks spent queuing 19311680SCurtis.Dunham@arm.comsystem.mem_ctrls.totMemAccLat 6782 # Total ticks spent from burst creation until serviced by the DRAM 19411680SCurtis.Dunham@arm.comsystem.mem_ctrls.totBusLat 1210 # Total ticks spent in databus transfers 19511680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgQLat 9.02 # Average queueing delay per DRAM burst 19611308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 19711680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgMemAccLat 28.02 # Average memory access latency per DRAM burst 19811680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgRdBW 1120.61 # Average DRAM read bandwidth in MiByte/s 19911308Santhony.gutierrez@amd.comsystem.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 20011680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgRdBWSys 1185.44 # Average system read bandwidth in MiByte/s 20111680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgWrBWSys 64.83 # Average system write bandwidth in MiByte/s 20211308Santhony.gutierrez@amd.comsystem.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 20311680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtil 8.75 # Data bus utilization in percentage 20411680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtilRead 8.75 # Data bus utilization in percentage for reads 20511308Santhony.gutierrez@amd.comsystem.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes 20611680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgRdQLen 1.20 # Average read queue length when enqueuing 20711680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgWrQLen 3.35 # Average write queue length when enqueuing 20811680SCurtis.Dunham@arm.comsystem.mem_ctrls.readRowHits 223 # Number of row buffer hits during reads 20911308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes 21011680SCurtis.Dunham@arm.comsystem.mem_ctrls.readRowHitRate 92.15 # Row buffer hit rate for reads 21111308Santhony.gutierrez@amd.comsystem.mem_ctrls.writeRowHitRate 0.00 # Row buffer hit rate for writes 21211680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgGap 50.78 # Average gap between requests 21311680SCurtis.Dunham@arm.comsystem.mem_ctrls.pageHitRate 87.11 # Row buffer hit rate, read and write combined 21411680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actEnergy 135660 # Energy for activate commands per rank (pJ) 21511680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.preEnergy 57960 # Energy for precharge commands per rank (pJ) 21611680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.readEnergy 2764608 # Energy for read commands per rank (pJ) 21711308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) 21811680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) 21911680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actBackEnergy 2757888 # Energy for active background per rank (pJ) 22011680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.preBackEnergy 44928 # Energy for precharge background per rank (pJ) 22111680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actPowerDownEnergy 3490680 # Energy for active power-down per rank (pJ) 22211680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.prePowerDownEnergy 384 # Energy for precharge power-down per rank (pJ) 22311680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 22411680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.totalEnergy 9866748 # Total energy per rank (pJ) 22511680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.averagePower 713.895377 # Core power per rank (mW) 22611680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.totalIdleTime 7568 # Total Idle time Per DRAM Rank 22711680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::IDLE 89 # Time in different power states 22811308Santhony.gutierrez@amd.comsystem.mem_ctrls_0.memoryStateTime::REF 260 # Time in different power states 22911680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states 23011680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN 1 # Time in different power states 23111680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT 5816 # Time in different power states 23211680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN 7655 # Time in different power states 23311308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) 23411308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) 23511308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) 23611308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) 23711680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) 23811680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actBackEnergy 112176 # Energy for active background per rank (pJ) 23911680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ) 24011680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) 24111680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.prePowerDownEnergy 2217600 # Energy for precharge power-down per rank (pJ) 24211680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 24311680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.totalEnergy 5939616 # Total energy per rank (pJ) 24411680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.averagePower 429.752985 # Core power per rank (mW) 24511680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.totalIdleTime 0 # Total Idle time Per DRAM Rank 24611308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states 24711308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::REF 260 # Time in different power states 24811680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states 24911680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN 5775 # Time in different power states 25011308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states 25111308Santhony.gutierrez@amd.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25211680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 25311308Santhony.gutierrez@amd.comsystem.ruby.clk_domain.clock 1 # Clock period in ticks 25411680SCurtis.Dunham@arm.comsystem.ruby.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 25511312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::bucket_size 2 25611312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::max_bucket 19 25711312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::samples 63 25811680SCurtis.Dunham@arm.comsystem.ruby.outstanding_req_hist_seqr::mean 12.873016 25911680SCurtis.Dunham@arm.comsystem.ruby.outstanding_req_hist_seqr::gmean 11.658152 26011680SCurtis.Dunham@arm.comsystem.ruby.outstanding_req_hist_seqr::stdev 4.202503 26111680SCurtis.Dunham@arm.comsystem.ruby.outstanding_req_hist_seqr | 1 1.59% 1.59% | 2 3.17% 4.76% | 2 3.17% 7.94% | 5 7.94% 15.87% | 4 6.35% 22.22% | 3 4.76% 26.98% | 5 7.94% 34.92% | 16 25.40% 60.32% | 25 39.68% 100.00% | 0 0.00% 100.00% 26211312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::total 63 26311312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr::bucket_size 2 26411312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_coalsr::max_bucket 19 26511680SCurtis.Dunham@arm.comsystem.ruby.outstanding_req_hist_coalsr::samples 872 26611680SCurtis.Dunham@arm.comsystem.ruby.outstanding_req_hist_coalsr::mean 2.547018 26711680SCurtis.Dunham@arm.comsystem.ruby.outstanding_req_hist_coalsr::gmean 2.158955 26811680SCurtis.Dunham@arm.comsystem.ruby.outstanding_req_hist_coalsr::stdev 1.537168 26911680SCurtis.Dunham@arm.comsystem.ruby.outstanding_req_hist_coalsr | 236 27.06% 27.06% | 460 52.75% 79.82% | 126 14.45% 94.27% | 40 4.59% 98.85% | 9 1.03% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 27011680SCurtis.Dunham@arm.comsystem.ruby.outstanding_req_hist_coalsr::total 872 27111312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::bucket_size 1024 27211312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::max_bucket 10239 27311312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::samples 48 27411680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::mean 3315.854167 27511680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::gmean 1841.298781 27611680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::stdev 1907.716848 27711680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr | 11 22.92% 22.92% | 3 6.25% 29.17% | 3 6.25% 35.42% | 7 14.58% 50.00% | 20 41.67% 91.67% | 4 8.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 27811312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::total 48 27911312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr::bucket_size 128 28011312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_coalsr::max_bucket 1279 28111680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_coalsr::samples 858 28211680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_coalsr::mean 215.358974 28311680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_coalsr::gmean 107.894342 28411680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_coalsr::stdev 237.470134 28511680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_coalsr | 573 66.78% 66.78% | 36 4.20% 70.98% | 111 12.94% 83.92% | 37 4.31% 88.23% | 24 2.80% 91.03% | 19 2.21% 93.24% | 32 3.73% 96.97% | 23 2.68% 99.65% | 3 0.35% 100.00% | 0 0.00% 100.00% 28611680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_coalsr::total 858 28711312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::bucket_size 1024 28811312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::max_bucket 10239 28911312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::samples 42 29011680SCurtis.Dunham@arm.comsystem.ruby.hit_latency_hist_seqr::mean 3644.142857 29111680SCurtis.Dunham@arm.comsystem.ruby.hit_latency_hist_seqr::gmean 2737.850881 29211680SCurtis.Dunham@arm.comsystem.ruby.hit_latency_hist_seqr::stdev 1757.652877 29311680SCurtis.Dunham@arm.comsystem.ruby.hit_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 20 47.62% 90.48% | 4 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 29411312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::total 42 29511312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::bucket_size 512 29611312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::max_bucket 5119 29711312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::samples 6 29811680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::mean 1017.833333 29911680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::gmean 114.584426 30011680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::stdev 1278.753677 30111680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 30211312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::total 6 30311312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr::bucket_size 128 30411312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_coalsr::max_bucket 1279 30511680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_coalsr::samples 858 30611680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_coalsr::mean 215.358974 30711680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_coalsr::gmean 107.894342 30811680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_coalsr::stdev 237.470134 30911680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_coalsr | 573 66.78% 66.78% | 36 4.20% 70.98% | 111 12.94% 83.92% | 37 4.31% 88.23% | 24 2.80% 91.03% | 19 2.21% 93.24% | 32 3.73% 96.97% | 23 2.68% 99.65% | 3 0.35% 100.00% | 0 0.00% 100.00% 31011680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_coalsr::total 858 31111312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.incomplete_times_seqr 6 31211308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits 31311308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_misses 45 # Number of cache demand misses 31411308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.demand_accesses 45 # Number of cache demand accesses 31511308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_data_array_writes 43 # number of data array writes 31611680SCurtis.Dunham@arm.comsystem.cp_cntrl0.L1D0cache.num_tag_array_reads 155 # number of tag array reads 31711308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D0cache.num_tag_array_writes 41 # number of tag array writes 31811308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits 31911680SCurtis.Dunham@arm.comsystem.cp_cntrl0.L1D1cache.demand_misses 45 # Number of cache demand misses 32011680SCurtis.Dunham@arm.comsystem.cp_cntrl0.L1D1cache.demand_accesses 45 # Number of cache demand accesses 32111680SCurtis.Dunham@arm.comsystem.cp_cntrl0.L1D1cache.num_data_array_writes 42 # number of data array writes 32211680SCurtis.Dunham@arm.comsystem.cp_cntrl0.L1D1cache.num_tag_array_reads 74 # number of tag array reads 32311680SCurtis.Dunham@arm.comsystem.cp_cntrl0.L1D1cache.num_tag_array_writes 42 # number of tag array writes 32411308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits 32511308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_misses 3 # Number of cache demand misses 32611308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.demand_accesses 3 # Number of cache demand accesses 32711308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L1Icache.num_tag_array_reads 3 # number of tag array reads 32811308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 32911680SCurtis.Dunham@arm.comsystem.cp_cntrl0.L2cache.demand_misses 93 # Number of cache demand misses 33011680SCurtis.Dunham@arm.comsystem.cp_cntrl0.L2cache.demand_accesses 93 # Number of cache demand accesses 33111308Santhony.gutierrez@amd.comsystem.cp_cntrl0.L2cache.num_data_array_reads 81 # number of data array reads 33211680SCurtis.Dunham@arm.comsystem.cp_cntrl0.L2cache.num_data_array_writes 85 # number of data array writes 33311680SCurtis.Dunham@arm.comsystem.cp_cntrl0.L2cache.num_tag_array_reads 372 # number of tag array reads 33411680SCurtis.Dunham@arm.comsystem.cp_cntrl0.L2cache.num_tag_array_writes 362 # number of tag array writes 33511860Sandreas.hansson@arm.comsystem.cp_cntrl0.mandatoryQueue.avg_buf_msgs 25.716177 # Average number of messages in buffer 33611860Sandreas.hansson@arm.comsystem.cp_cntrl0.mandatoryQueue.avg_stall_time 2962.798293 # Average number of cycles messages are stalled in this MB 33711860Sandreas.hansson@arm.comsystem.cp_cntrl0.probeToCore.avg_buf_msgs 0.015627 # Average number of messages in buffer 33811860Sandreas.hansson@arm.comsystem.cp_cntrl0.probeToCore.avg_stall_time 33.503111 # Average number of cycles messages are stalled in this MB 33911860Sandreas.hansson@arm.comsystem.cp_cntrl0.requestFromCore.avg_buf_msgs 0.169512 # Average number of messages in buffer 34011860Sandreas.hansson@arm.comsystem.cp_cntrl0.requestFromCore.avg_stall_time 14.915352 # Average number of cycles messages are stalled in this MB 34111860Sandreas.hansson@arm.comsystem.cp_cntrl0.responseFromCore.avg_buf_msgs 0.311460 # Average number of messages in buffer 34211860Sandreas.hansson@arm.comsystem.cp_cntrl0.responseFromCore.avg_stall_time 14.764506 # Average number of cycles messages are stalled in this MB 34311860Sandreas.hansson@arm.comsystem.cp_cntrl0.responseToCore.avg_buf_msgs 0.011069 # Average number of messages in buffer 34411860Sandreas.hansson@arm.comsystem.cp_cntrl0.responseToCore.avg_stall_time 14.645999 # Average number of cycles messages are stalled in this MB 34511680SCurtis.Dunham@arm.comsystem.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 34611680SCurtis.Dunham@arm.comsystem.cp_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load 34711680SCurtis.Dunham@arm.comsystem.cp_cntrl0.sequencer.store_waiting_on_store 4 # Number of times a store aliased with a pending store 34811680SCurtis.Dunham@arm.comsystem.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 34911308Santhony.gutierrez@amd.comsystem.cp_cntrl0.sequencer1.store_waiting_on_store 4 # Number of times a store aliased with a pending store 35011860Sandreas.hansson@arm.comsystem.cp_cntrl0.unblockFromCore.avg_buf_msgs 0.088699 # Average number of messages in buffer 35111860Sandreas.hansson@arm.comsystem.cp_cntrl0.unblockFromCore.avg_stall_time 14.634279 # Average number of cycles messages are stalled in this MB 35211680SCurtis.Dunham@arm.comsystem.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 35311680SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 35411308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits 35511308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses 35611308Santhony.gutierrez@amd.comsystem.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses 35711680SCurtis.Dunham@arm.comsystem.dir_cntrl0.L3CacheMemory.num_data_array_writes 365 # number of data array writes 35811680SCurtis.Dunham@arm.comsystem.dir_cntrl0.L3CacheMemory.num_tag_array_reads 372 # number of tag array reads 35911680SCurtis.Dunham@arm.comsystem.dir_cntrl0.L3CacheMemory.num_tag_array_writes 369 # number of tag array writes 36011680SCurtis.Dunham@arm.comsystem.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 9126 # number of stalls caused by tag array 36111680SCurtis.Dunham@arm.comsystem.dir_cntrl0.L3CacheMemory.num_data_array_stalls 4922 # number of stalls caused by data array 36211860Sandreas.hansson@arm.comsystem.dir_cntrl0.L3triggerQueue.avg_buf_msgs 0.048835 # Average number of messages in buffer 36311860Sandreas.hansson@arm.comsystem.dir_cntrl0.L3triggerQueue.avg_stall_time 12.961945 # Average number of cycles messages are stalled in this MB 36411860Sandreas.hansson@arm.comsystem.dir_cntrl0.probeToCore.avg_buf_msgs 0.653306 # Average number of messages in buffer 36511860Sandreas.hansson@arm.comsystem.dir_cntrl0.probeToCore.avg_stall_time 29.756909 # Average number of cycles messages are stalled in this MB 36611860Sandreas.hansson@arm.comsystem.dir_cntrl0.requestFromCores.avg_buf_msgs 4.168499 # Average number of messages in buffer 36711860Sandreas.hansson@arm.comsystem.dir_cntrl0.requestFromCores.avg_stall_time 219.183837 # Average number of cycles messages are stalled in this MB 36811860Sandreas.hansson@arm.comsystem.dir_cntrl0.requestFromCores.num_msg_stalls 6 # Number of times messages were stalled 36911860Sandreas.hansson@arm.comsystem.dir_cntrl0.responseFromCores.avg_buf_msgs 0.236001 # Average number of messages in buffer 37011860Sandreas.hansson@arm.comsystem.dir_cntrl0.responseFromCores.avg_stall_time 44.490812 # Average number of cycles messages are stalled in this MB 37111860Sandreas.hansson@arm.comsystem.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.033280 # Average number of messages in buffer 37211860Sandreas.hansson@arm.comsystem.dir_cntrl0.responseFromMemory.avg_stall_time 1.594198 # Average number of cycles messages are stalled in this MB 37311860Sandreas.hansson@arm.comsystem.dir_cntrl0.responseToCore.avg_buf_msgs 0.651932 # Average number of messages in buffer 37411860Sandreas.hansson@arm.comsystem.dir_cntrl0.responseToCore.avg_stall_time 21.888945 # Average number of cycles messages are stalled in this MB 37511860Sandreas.hansson@arm.comsystem.dir_cntrl0.triggerQueue.avg_buf_msgs 0.808711 # Average number of messages in buffer 37611860Sandreas.hansson@arm.comsystem.dir_cntrl0.triggerQueue.avg_stall_time 28.172406 # Average number of cycles messages are stalled in this MB 37711860Sandreas.hansson@arm.comsystem.dir_cntrl0.unblockFromCores.avg_buf_msgs 0.021343 # Average number of messages in buffer 37811860Sandreas.hansson@arm.comsystem.dir_cntrl0.unblockFromCores.avg_stall_time 89.749240 # Average number of cycles messages are stalled in this MB 37911680SCurtis.Dunham@arm.comsystem.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 38011860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers000.avg_buf_msgs 0.026914 # Average number of messages in buffer 38111860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers000.avg_stall_time 83.794892 # Average number of cycles messages are stalled in this MB 38211860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers002.avg_buf_msgs 0.026697 # Average number of messages in buffer 38311860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers002.avg_stall_time 39.227029 # Average number of cycles messages are stalled in this MB 38411860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers004.avg_buf_msgs 0.021343 # Average number of messages in buffer 38511860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers004.avg_stall_time 88.782810 # Average number of cycles messages are stalled in this MB 38611860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers005.avg_buf_msgs 0.015627 # Average number of messages in buffer 38711860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers005.avg_stall_time 30.553683 # Average number of cycles messages are stalled in this MB 38811860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers007.avg_buf_msgs 0.011069 # Average number of messages in buffer 38911860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers007.avg_stall_time 11.722616 # Average number of cycles messages are stalled in this MB 39011860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers015.avg_buf_msgs 0.006077 # Average number of messages in buffer 39111860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers015.avg_stall_time 30.746563 # Average number of cycles messages are stalled in this MB 39211860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers017.avg_buf_msgs 0.015627 # Average number of messages in buffer 39311860Sandreas.hansson@arm.comsystem.ruby.network.ext_links00.int_node.port_buffers017.avg_stall_time 30.419114 # Average number of cycles messages are stalled in this MB 39411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 39511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.percent_links_utilized 0.199915 39611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_count.Control::0 300 39711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_count.Request_Control::0 372 39811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_count.Response_Data::2 383 39911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_count.Response_Control::2 217 40011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_count.Writeback_Data::2 67 40111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_count.Writeback_Control::2 71 40211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_count.Unblock_Control::4 295 40311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_bytes.Control::0 2400 40411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_bytes.Request_Control::0 2976 40511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_bytes.Response_Data::2 27576 40611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2 1736 40711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4824 40811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 568 40911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2360 41011860Sandreas.hansson@arm.comsystem.ruby.network.ext_links01.int_node.port_buffers000.avg_buf_msgs 0.015627 # Average number of messages in buffer 41111860Sandreas.hansson@arm.comsystem.ruby.network.ext_links01.int_node.port_buffers000.avg_stall_time 32.520113 # Average number of cycles messages are stalled in this MB 41211860Sandreas.hansson@arm.comsystem.ruby.network.ext_links01.int_node.port_buffers002.avg_buf_msgs 0.011069 # Average number of messages in buffer 41311860Sandreas.hansson@arm.comsystem.ruby.network.ext_links01.int_node.port_buffers002.avg_stall_time 13.671683 # Average number of cycles messages are stalled in this MB 41411860Sandreas.hansson@arm.comsystem.ruby.network.ext_links01.int_node.port_buffers003.avg_buf_msgs 0.011214 # Average number of messages in buffer 41511860Sandreas.hansson@arm.comsystem.ruby.network.ext_links01.int_node.port_buffers003.avg_stall_time 15.908552 # Average number of cycles messages are stalled in this MB 41611860Sandreas.hansson@arm.comsystem.ruby.network.ext_links01.int_node.port_buffers005.avg_buf_msgs 0.020764 # Average number of messages in buffer 41711860Sandreas.hansson@arm.comsystem.ruby.network.ext_links01.int_node.port_buffers005.avg_stall_time 15.747649 # Average number of cycles messages are stalled in this MB 41811860Sandreas.hansson@arm.comsystem.ruby.network.ext_links01.int_node.port_buffers007.avg_buf_msgs 0.005860 # Average number of messages in buffer 41911860Sandreas.hansson@arm.comsystem.ruby.network.ext_links01.int_node.port_buffers007.avg_stall_time 15.608740 # Average number of cycles messages are stalled in this MB 42011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 42111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.percent_links_utilized 0.123680 42211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_count.Control::0 216 42311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_count.Request_Control::0 155 42411308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links01.int_node.msg_count.Response_Data::2 95 42511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_count.Response_Control::2 207 42611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_count.Writeback_Data::2 67 42711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_count.Writeback_Control::2 71 42811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_count.Unblock_Control::4 81 42911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_bytes.Control::0 1728 43011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_bytes.Request_Control::0 1240 43111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links01.int_node.msg_bytes.Response_Data::2 6840 43211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_bytes.Response_Control::2 1656 43311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Data::2 4824 43411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Control::2 568 43511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.msg_bytes.Unblock_Control::4 648 43611308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 43711308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 43811308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 43911680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.L1cache.num_data_array_reads 16 # number of data array reads 44011680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.L1cache.num_data_array_writes 112 # number of data array writes 44111680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.L1cache.num_tag_array_reads 309 # number of tag array reads 44211680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.L1cache.num_tag_array_writes 300 # number of tag array writes 44311680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.L1cache.num_tag_array_stalls 28 # number of stalls caused by tag array 44411680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 44511308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP 44611680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers 44711308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 44811680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.coalescer.gpu_ld_misses 1 # loads that miss in the GPU 44911308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP 45011680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 74 # TCP to TCP store transfers 45111308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 45211680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.coalescer.gpu_st_misses 19 # stores that miss in the GPU 45311308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 45411308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 45511308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 45611308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU 45711308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 45811308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 45911308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 46011308Santhony.gutierrez@amd.comsystem.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU 46111860Sandreas.hansson@arm.comsystem.tcp_cntrl0.mandatoryQueue.avg_buf_msgs 0.009767 # Average number of messages in buffer 46211860Sandreas.hansson@arm.comsystem.tcp_cntrl0.mandatoryQueue.avg_stall_time 1.140790 # Average number of cycles messages are stalled in this MB 46311860Sandreas.hansson@arm.comsystem.tcp_cntrl0.probeToTCP.avg_buf_msgs 0.007741 # Average number of messages in buffer 46411860Sandreas.hansson@arm.comsystem.tcp_cntrl0.probeToTCP.avg_stall_time 6.886268 # Average number of cycles messages are stalled in this MB 46511860Sandreas.hansson@arm.comsystem.tcp_cntrl0.requestFromTCP.avg_buf_msgs 0.308928 # Average number of messages in buffer 46611860Sandreas.hansson@arm.comsystem.tcp_cntrl0.requestFromTCP.avg_stall_time 39.646940 # Average number of cycles messages are stalled in this MB 46711860Sandreas.hansson@arm.comsystem.tcp_cntrl0.responseFromTCP.avg_buf_msgs 0.289249 # Average number of messages in buffer 46811860Sandreas.hansson@arm.comsystem.tcp_cntrl0.responseFromTCP.avg_stall_time 38.260744 # Average number of cycles messages are stalled in this MB 46911860Sandreas.hansson@arm.comsystem.tcp_cntrl0.responseToTCP.avg_buf_msgs 0.007597 # Average number of messages in buffer 47011860Sandreas.hansson@arm.comsystem.tcp_cntrl0.responseToTCP.avg_stall_time 2.919621 # Average number of cycles messages are stalled in this MB 47111680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 47211860Sandreas.hansson@arm.comsystem.tcp_cntrl0.unblockFromCore.avg_buf_msgs 0.298076 # Average number of messages in buffer 47311860Sandreas.hansson@arm.comsystem.tcp_cntrl0.unblockFromCore.avg_stall_time 38.422804 # Average number of cycles messages are stalled in this MB 47411680SCurtis.Dunham@arm.comsystem.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 47511860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers001.avg_buf_msgs 0.007235 # Average number of messages in buffer 47611860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers001.avg_stall_time 5.756909 # Average number of cycles messages are stalled in this MB 47711860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers003.avg_buf_msgs 0.007452 # Average number of messages in buffer 47811860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers003.avg_stall_time 1.927073 # Average number of cycles messages are stalled in this MB 47911860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers005.avg_buf_msgs 0.007018 # Average number of messages in buffer 48011860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers005.avg_stall_time 5.309796 # Average number of cycles messages are stalled in this MB 48111860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers007.avg_buf_msgs 0.007018 # Average number of messages in buffer 48211860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers007.avg_stall_time 1.940095 # Average number of cycles messages are stalled in this MB 48311860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers009.avg_buf_msgs 0.006656 # Average number of messages in buffer 48411860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers009.avg_stall_time 5.861091 # Average number of cycles messages are stalled in this MB 48511860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers011.avg_buf_msgs 0.006945 # Average number of messages in buffer 48611860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers011.avg_stall_time 1.961800 # Average number of cycles messages are stalled in this MB 48711860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers013.avg_buf_msgs 0.006222 # Average number of messages in buffer 48811860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers013.avg_stall_time 5.483432 # Average number of cycles messages are stalled in this MB 48911860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers015.avg_buf_msgs 0.006367 # Average number of messages in buffer 49011860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers015.avg_stall_time 1.879323 # Average number of cycles messages are stalled in this MB 49111860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers017.avg_buf_msgs 0.007524 # Average number of messages in buffer 49211860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers017.avg_stall_time 5.492114 # Average number of cycles messages are stalled in this MB 49311860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers019.avg_buf_msgs 0.007452 # Average number of messages in buffer 49411860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers019.avg_stall_time 1.931414 # Average number of cycles messages are stalled in this MB 49511860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers021.avg_buf_msgs 0.006367 # Average number of messages in buffer 49611860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers021.avg_stall_time 5.539864 # Average number of cycles messages are stalled in this MB 49711860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers023.avg_buf_msgs 0.006656 # Average number of messages in buffer 49811860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers023.avg_stall_time 1.957459 # Average number of cycles messages are stalled in this MB 49911860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers025.avg_buf_msgs 0.008031 # Average number of messages in buffer 50011860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers025.avg_stall_time 5.544205 # Average number of cycles messages are stalled in this MB 50111860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers027.avg_buf_msgs 0.008320 # Average number of messages in buffer 50211860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers027.avg_stall_time 1.947041 # Average number of cycles messages are stalled in this MB 50311860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers029.avg_buf_msgs 0.006439 # Average number of messages in buffer 50411860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers029.avg_stall_time 5.457387 # Average number of cycles messages are stalled in this MB 50511860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers031.avg_buf_msgs 0.006728 # Average number of messages in buffer 50611860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers031.avg_stall_time 1.901027 # Average number of cycles messages are stalled in this MB 50711860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers036.avg_buf_msgs 0.006077 # Average number of messages in buffer 50811860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers036.avg_stall_time 32.725438 # Average number of cycles messages are stalled in this MB 50911860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers037.avg_buf_msgs 0.059543 # Average number of messages in buffer 51011860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers037.avg_stall_time 41.896903 # Average number of cycles messages are stalled in this MB 51111860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers038.avg_buf_msgs 0.015627 # Average number of messages in buffer 51211860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers038.avg_stall_time 32.376863 # Average number of cycles messages are stalled in this MB 51311860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers039.avg_buf_msgs 0.056794 # Average number of messages in buffer 51411860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers039.avg_stall_time 40.742295 # Average number of cycles messages are stalled in this MB 51511860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers041.avg_buf_msgs 0.058602 # Average number of messages in buffer 51611860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers041.avg_stall_time 41.125452 # Average number of cycles messages are stalled in this MB 51711860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers043.avg_buf_msgs 0.000796 # Average number of messages in buffer 51811860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers043.avg_stall_time 2.867168 # Average number of cycles messages are stalled in this MB 51911860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers045.avg_buf_msgs 0.000868 # Average number of messages in buffer 52011860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers045.avg_stall_time 1.317610 # Average number of cycles messages are stalled in this MB 52111860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers047.avg_buf_msgs 0.000796 # Average number of messages in buffer 52211860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers047.avg_stall_time 3.139343 # Average number of cycles messages are stalled in this MB 52311860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers049.avg_buf_msgs 0.000868 # Average number of messages in buffer 52411860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers049.avg_stall_time 1.151208 # Average number of cycles messages are stalled in this MB 52511860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers050.avg_buf_msgs 0.015700 # Average number of messages in buffer 52611860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers050.avg_stall_time 119.555564 # Average number of cycles messages are stalled in this MB 52711860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers052.avg_buf_msgs 0.005933 # Average number of messages in buffer 52811860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers052.avg_stall_time 118.925264 # Average number of cycles messages are stalled in this MB 52911860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers054.avg_buf_msgs 0.015483 # Average number of messages in buffer 53011860Sandreas.hansson@arm.comsystem.ruby.network.ext_links02.int_node.port_buffers054.avg_stall_time 117.253220 # Average number of cycles messages are stalled in this MB 53111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 53211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.percent_links_utilized 0.172944 53311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_count.Control::0 84 53411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_count.Control::1 789 53511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_count.Request_Control::0 217 53611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_count.Request_Control::1 823 53711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_count.Response_Data::2 288 53811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_count.Response_Data::3 1594 53911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.msg_count.Response_Control::2 10 54011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.msg_count.Response_Control::3 2 54111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::4 214 54211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::5 810 54311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_bytes.Control::0 672 54411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_bytes.Control::1 6312 54511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::0 1736 54611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::1 6584 54711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::2 20736 54811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::3 114768 54911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::2 80 55011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::3 16 55111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::4 1712 55211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::5 6480 55311308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 55411308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 55511308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses 55611680SCurtis.Dunham@arm.comsystem.tcp_cntrl1.L1cache.num_data_array_reads 11 # number of data array reads 55711308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.L1cache.num_data_array_writes 108 # number of data array writes 55811680SCurtis.Dunham@arm.comsystem.tcp_cntrl1.L1cache.num_tag_array_reads 298 # number of tag array reads 55911680SCurtis.Dunham@arm.comsystem.tcp_cntrl1.L1cache.num_tag_array_writes 285 # number of tag array writes 56011680SCurtis.Dunham@arm.comsystem.tcp_cntrl1.L1cache.num_tag_array_stalls 43 # number of stalls caused by tag array 56111680SCurtis.Dunham@arm.comsystem.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 56211308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP 56311680SCurtis.Dunham@arm.comsystem.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers 56411308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 56511680SCurtis.Dunham@arm.comsystem.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 56611680SCurtis.Dunham@arm.comsystem.tcp_cntrl1.coalescer.gpu_tcp_st_hits 11 # stores that hit in the TCP 56711680SCurtis.Dunham@arm.comsystem.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers 56811308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 56911308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.gpu_st_misses 20 # stores that miss in the GPU 57011308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 57111308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 57211308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 57311308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU 57411308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 57511308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 57611308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 57711308Santhony.gutierrez@amd.comsystem.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU 57811860Sandreas.hansson@arm.comsystem.tcp_cntrl1.mandatoryQueue.avg_buf_msgs 0.010491 # Average number of messages in buffer 57911860Sandreas.hansson@arm.comsystem.tcp_cntrl1.mandatoryQueue.avg_stall_time 1.432571 # Average number of cycles messages are stalled in this MB 58011860Sandreas.hansson@arm.comsystem.tcp_cntrl1.probeToTCP.avg_buf_msgs 0.007524 # Average number of messages in buffer 58111860Sandreas.hansson@arm.comsystem.tcp_cntrl1.probeToTCP.avg_stall_time 6.242584 # Average number of cycles messages are stalled in this MB 58211860Sandreas.hansson@arm.comsystem.tcp_cntrl1.requestFromTCP.avg_buf_msgs 0.289394 # Average number of messages in buffer 58311860Sandreas.hansson@arm.comsystem.tcp_cntrl1.requestFromTCP.avg_stall_time 39.762697 # Average number of cycles messages are stalled in this MB 58411860Sandreas.hansson@arm.comsystem.tcp_cntrl1.responseFromTCP.avg_buf_msgs 0.280712 # Average number of messages in buffer 58511860Sandreas.hansson@arm.comsystem.tcp_cntrl1.responseFromTCP.avg_stall_time 35.279988 # Average number of cycles messages are stalled in this MB 58611860Sandreas.hansson@arm.comsystem.tcp_cntrl1.responseToTCP.avg_buf_msgs 0.007235 # Average number of messages in buffer 58711860Sandreas.hansson@arm.comsystem.tcp_cntrl1.responseToTCP.avg_stall_time 2.914484 # Average number of cycles messages are stalled in this MB 58811680SCurtis.Dunham@arm.comsystem.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 58911860Sandreas.hansson@arm.comsystem.tcp_cntrl1.unblockFromCore.avg_buf_msgs 0.280712 # Average number of messages in buffer 59011860Sandreas.hansson@arm.comsystem.tcp_cntrl1.unblockFromCore.avg_stall_time 38.683259 # Average number of cycles messages are stalled in this MB 59111680SCurtis.Dunham@arm.comsystem.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 59211308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.L1cache.demand_hits 0 # Number of cache demand hits 59311308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.L1cache.demand_misses 0 # Number of cache demand misses 59411308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.L1cache.demand_accesses 0 # Number of cache demand accesses 59511680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.L1cache.num_data_array_reads 11 # number of data array reads 59611680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.L1cache.num_data_array_writes 106 # number of data array writes 59711680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.L1cache.num_tag_array_reads 286 # number of tag array reads 59811680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.L1cache.num_tag_array_writes 275 # number of tag array writes 59911680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.L1cache.num_tag_array_stalls 42 # number of stalls caused by tag array 60011680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 60111680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP 60211680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers 60311308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 60411680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.coalescer.gpu_ld_misses 1 # loads that miss in the GPU 60511680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP 60611680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers 60711308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 60811308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.coalescer.gpu_st_misses 18 # stores that miss in the GPU 60911308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 61011308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 61111308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 61211308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.coalescer.cp_ld_misses 0 # loads that miss in the GPU 61311308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 61411308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 61511308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 61611308Santhony.gutierrez@amd.comsystem.tcp_cntrl2.coalescer.cp_st_misses 0 # stores that miss in the GPU 61711860Sandreas.hansson@arm.comsystem.tcp_cntrl2.mandatoryQueue.avg_buf_msgs 0.010418 # Average number of messages in buffer 61811860Sandreas.hansson@arm.comsystem.tcp_cntrl2.mandatoryQueue.avg_stall_time 1.277312 # Average number of cycles messages are stalled in this MB 61911860Sandreas.hansson@arm.comsystem.tcp_cntrl2.probeToTCP.avg_buf_msgs 0.006728 # Average number of messages in buffer 62011860Sandreas.hansson@arm.comsystem.tcp_cntrl2.probeToTCP.avg_stall_time 6.844596 # Average number of cycles messages are stalled in this MB 62111860Sandreas.hansson@arm.comsystem.tcp_cntrl2.requestFromTCP.avg_buf_msgs 0.280712 # Average number of messages in buffer 62211860Sandreas.hansson@arm.comsystem.tcp_cntrl2.requestFromTCP.avg_stall_time 39.878455 # Average number of cycles messages are stalled in this MB 62311860Sandreas.hansson@arm.comsystem.tcp_cntrl2.responseFromTCP.avg_buf_msgs 0.266242 # Average number of messages in buffer 62411860Sandreas.hansson@arm.comsystem.tcp_cntrl2.responseFromTCP.avg_stall_time 38.955289 # Average number of cycles messages are stalled in this MB 62511860Sandreas.hansson@arm.comsystem.tcp_cntrl2.responseToTCP.avg_buf_msgs 0.007307 # Average number of messages in buffer 62611860Sandreas.hansson@arm.comsystem.tcp_cntrl2.responseToTCP.avg_stall_time 2.965417 # Average number of cycles messages are stalled in this MB 62711680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 62811860Sandreas.hansson@arm.comsystem.tcp_cntrl2.unblockFromCore.avg_buf_msgs 0.277818 # Average number of messages in buffer 62911860Sandreas.hansson@arm.comsystem.tcp_cntrl2.unblockFromCore.avg_stall_time 39.117349 # Average number of cycles messages are stalled in this MB 63011680SCurtis.Dunham@arm.comsystem.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 63111308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.L1cache.demand_hits 0 # Number of cache demand hits 63211308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.L1cache.demand_misses 0 # Number of cache demand misses 63311308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.L1cache.demand_accesses 0 # Number of cache demand accesses 63411680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.L1cache.num_data_array_reads 8 # number of data array reads 63511680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.L1cache.num_data_array_writes 95 # number of data array writes 63611680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.L1cache.num_tag_array_reads 260 # number of tag array reads 63711680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.L1cache.num_tag_array_writes 253 # number of tag array writes 63811680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.L1cache.num_tag_array_stalls 29 # number of stalls caused by tag array 63911308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.L1cache.num_data_array_stalls 3 # number of stalls caused by data array 64011680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 64111308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP 64211680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers 12 # TCP to TCP load transfers 64311308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 64411308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 64511680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP 64611680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.coalescer.gpu_tcp_st_transfers 59 # TCP to TCP store transfers 64711308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 64811680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.coalescer.gpu_st_misses 17 # stores that miss in the GPU 64911308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 65011308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 65111308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 65211308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.cp_ld_misses 0 # loads that miss in the GPU 65311308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 65411308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 65511308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 65611308Santhony.gutierrez@amd.comsystem.tcp_cntrl3.coalescer.cp_st_misses 0 # stores that miss in the GPU 65711860Sandreas.hansson@arm.comsystem.tcp_cntrl3.mandatoryQueue.avg_buf_msgs 0.008465 # Average number of messages in buffer 65811860Sandreas.hansson@arm.comsystem.tcp_cntrl3.mandatoryQueue.avg_stall_time 1.170164 # Average number of cycles messages are stalled in this MB 65911860Sandreas.hansson@arm.comsystem.tcp_cntrl3.probeToTCP.avg_buf_msgs 0.006728 # Average number of messages in buffer 66011860Sandreas.hansson@arm.comsystem.tcp_cntrl3.probeToTCP.avg_stall_time 6.502170 # Average number of cycles messages are stalled in this MB 66111860Sandreas.hansson@arm.comsystem.tcp_cntrl3.requestFromTCP.avg_buf_msgs 0.261684 # Average number of messages in buffer 66211860Sandreas.hansson@arm.comsystem.tcp_cntrl3.requestFromTCP.avg_stall_time 39.039213 # Average number of cycles messages are stalled in this MB 66311860Sandreas.hansson@arm.comsystem.tcp_cntrl3.responseFromTCP.avg_buf_msgs 0.247504 # Average number of messages in buffer 66411860Sandreas.hansson@arm.comsystem.tcp_cntrl3.responseFromTCP.avg_stall_time 36.437563 # Average number of cycles messages are stalled in this MB 66511860Sandreas.hansson@arm.comsystem.tcp_cntrl3.responseToTCP.avg_buf_msgs 0.006801 # Average number of messages in buffer 66611860Sandreas.hansson@arm.comsystem.tcp_cntrl3.responseToTCP.avg_stall_time 2.855954 # Average number of cycles messages are stalled in this MB 66711680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 66811860Sandreas.hansson@arm.comsystem.tcp_cntrl3.unblockFromCore.avg_buf_msgs 0.254666 # Average number of messages in buffer 66911860Sandreas.hansson@arm.comsystem.tcp_cntrl3.unblockFromCore.avg_stall_time 37.467805 # Average number of cycles messages are stalled in this MB 67011680SCurtis.Dunham@arm.comsystem.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 67111308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.L1cache.demand_hits 0 # Number of cache demand hits 67211308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.L1cache.demand_misses 0 # Number of cache demand misses 67311308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.L1cache.demand_accesses 0 # Number of cache demand accesses 67411680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.L1cache.num_data_array_reads 16 # number of data array reads 67511680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.L1cache.num_data_array_writes 117 # number of data array writes 67611680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.L1cache.num_tag_array_reads 309 # number of tag array reads 67711680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.L1cache.num_tag_array_writes 299 # number of tag array writes 67811680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.L1cache.num_tag_array_stalls 31 # number of stalls caused by tag array 67911680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.L1cache.num_data_array_stalls 4 # number of stalls caused by data array 68011680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 68111680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP 68211680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers 5 # TCP to TCP load transfers 68311308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 68411308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 68511680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP 68611680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.coalescer.gpu_tcp_st_transfers 72 # TCP to TCP store transfers 68711308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 68811308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.gpu_st_misses 26 # stores that miss in the GPU 68911308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 69011308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 69111308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 69211308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.cp_ld_misses 0 # loads that miss in the GPU 69311308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 69411308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 69511308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 69611308Santhony.gutierrez@amd.comsystem.tcp_cntrl4.coalescer.cp_st_misses 0 # stores that miss in the GPU 69711860Sandreas.hansson@arm.comsystem.tcp_cntrl4.mandatoryQueue.avg_buf_msgs 0.009478 # Average number of messages in buffer 69811860Sandreas.hansson@arm.comsystem.tcp_cntrl4.mandatoryQueue.avg_stall_time 1.107365 # Average number of cycles messages are stalled in this MB 69911860Sandreas.hansson@arm.comsystem.tcp_cntrl4.probeToTCP.avg_buf_msgs 0.008031 # Average number of messages in buffer 70011860Sandreas.hansson@arm.comsystem.tcp_cntrl4.probeToTCP.avg_stall_time 6.466141 # Average number of cycles messages are stalled in this MB 70111860Sandreas.hansson@arm.comsystem.tcp_cntrl4.requestFromTCP.avg_buf_msgs 0.298076 # Average number of messages in buffer 70211860Sandreas.hansson@arm.comsystem.tcp_cntrl4.requestFromTCP.avg_stall_time 39.733758 # Average number of cycles messages are stalled in this MB 70311860Sandreas.hansson@arm.comsystem.tcp_cntrl4.responseFromTCP.avg_buf_msgs 0.300969 # Average number of messages in buffer 70411860Sandreas.hansson@arm.comsystem.tcp_cntrl4.responseFromTCP.avg_stall_time 36.495442 # Average number of cycles messages are stalled in this MB 70511860Sandreas.hansson@arm.comsystem.tcp_cntrl4.responseToTCP.avg_buf_msgs 0.008175 # Average number of messages in buffer 70611860Sandreas.hansson@arm.comsystem.tcp_cntrl4.responseToTCP.avg_stall_time 2.934380 # Average number of cycles messages are stalled in this MB 70711680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 70811860Sandreas.hansson@arm.comsystem.tcp_cntrl4.unblockFromCore.avg_buf_msgs 0.298076 # Average number of messages in buffer 70911860Sandreas.hansson@arm.comsystem.tcp_cntrl4.unblockFromCore.avg_stall_time 38.509622 # Average number of cycles messages are stalled in this MB 71011680SCurtis.Dunham@arm.comsystem.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 71111308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.L1cache.demand_hits 0 # Number of cache demand hits 71211308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.L1cache.demand_misses 0 # Number of cache demand misses 71311308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.L1cache.demand_accesses 0 # Number of cache demand accesses 71411680SCurtis.Dunham@arm.comsystem.tcp_cntrl5.L1cache.num_data_array_reads 9 # number of data array reads 71511680SCurtis.Dunham@arm.comsystem.tcp_cntrl5.L1cache.num_data_array_writes 101 # number of data array writes 71611680SCurtis.Dunham@arm.comsystem.tcp_cntrl5.L1cache.num_tag_array_reads 276 # number of tag array reads 71711680SCurtis.Dunham@arm.comsystem.tcp_cntrl5.L1cache.num_tag_array_writes 266 # number of tag array writes 71811680SCurtis.Dunham@arm.comsystem.tcp_cntrl5.L1cache.num_tag_array_stalls 22 # number of stalls caused by tag array 71911680SCurtis.Dunham@arm.comsystem.tcp_cntrl5.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 72011308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP 72111680SCurtis.Dunham@arm.comsystem.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers 3 # TCP to TCP load transfers 72211308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 72311308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 72411308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.gpu_tcp_st_hits 8 # stores that hit in the TCP 72511680SCurtis.Dunham@arm.comsystem.tcp_cntrl5.coalescer.gpu_tcp_st_transfers 67 # TCP to TCP store transfers 72611308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 72711680SCurtis.Dunham@arm.comsystem.tcp_cntrl5.coalescer.gpu_st_misses 22 # stores that miss in the GPU 72811308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 72911308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 73011308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 73111308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.cp_ld_misses 0 # loads that miss in the GPU 73211308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 73311308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 73411308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 73511308Santhony.gutierrez@amd.comsystem.tcp_cntrl5.coalescer.cp_st_misses 0 # stores that miss in the GPU 73611860Sandreas.hansson@arm.comsystem.tcp_cntrl5.mandatoryQueue.avg_buf_msgs 0.008465 # Average number of messages in buffer 73711860Sandreas.hansson@arm.comsystem.tcp_cntrl5.mandatoryQueue.avg_stall_time 1.079728 # Average number of cycles messages are stalled in this MB 73811860Sandreas.hansson@arm.comsystem.tcp_cntrl5.probeToTCP.avg_buf_msgs 0.006511 # Average number of messages in buffer 73911860Sandreas.hansson@arm.comsystem.tcp_cntrl5.probeToTCP.avg_stall_time 6.478585 # Average number of cycles messages are stalled in this MB 74011860Sandreas.hansson@arm.comsystem.tcp_cntrl5.requestFromTCP.avg_buf_msgs 0.269136 # Average number of messages in buffer 74111860Sandreas.hansson@arm.comsystem.tcp_cntrl5.requestFromTCP.avg_stall_time 39.849515 # Average number of cycles messages are stalled in this MB 74211860Sandreas.hansson@arm.comsystem.tcp_cntrl5.responseFromTCP.avg_buf_msgs 0.254015 # Average number of messages in buffer 74311860Sandreas.hansson@arm.comsystem.tcp_cntrl5.responseFromTCP.avg_stall_time 36.813775 # Average number of cycles messages are stalled in this MB 74411860Sandreas.hansson@arm.comsystem.tcp_cntrl5.responseToTCP.avg_buf_msgs 0.006945 # Average number of messages in buffer 74511860Sandreas.hansson@arm.comsystem.tcp_cntrl5.responseToTCP.avg_stall_time 2.959991 # Average number of cycles messages are stalled in this MB 74611680SCurtis.Dunham@arm.comsystem.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 74711860Sandreas.hansson@arm.comsystem.tcp_cntrl5.unblockFromCore.avg_buf_msgs 0.266242 # Average number of messages in buffer 74811860Sandreas.hansson@arm.comsystem.tcp_cntrl5.unblockFromCore.avg_stall_time 39.030531 # Average number of cycles messages are stalled in this MB 74911680SCurtis.Dunham@arm.comsystem.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 75011308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.L1cache.demand_hits 0 # Number of cache demand hits 75111308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.L1cache.demand_misses 0 # Number of cache demand misses 75211308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.L1cache.demand_accesses 0 # Number of cache demand accesses 75311680SCurtis.Dunham@arm.comsystem.tcp_cntrl6.L1cache.num_data_array_reads 15 # number of data array reads 75411680SCurtis.Dunham@arm.comsystem.tcp_cntrl6.L1cache.num_data_array_writes 120 # number of data array writes 75511680SCurtis.Dunham@arm.comsystem.tcp_cntrl6.L1cache.num_tag_array_reads 336 # number of tag array reads 75611680SCurtis.Dunham@arm.comsystem.tcp_cntrl6.L1cache.num_tag_array_writes 330 # number of tag array writes 75711680SCurtis.Dunham@arm.comsystem.tcp_cntrl6.L1cache.num_tag_array_stalls 44 # number of stalls caused by tag array 75811680SCurtis.Dunham@arm.comsystem.tcp_cntrl6.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 75911308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP 76011680SCurtis.Dunham@arm.comsystem.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers 76111308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 76211308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.gpu_ld_misses 1 # loads that miss in the GPU 76311680SCurtis.Dunham@arm.comsystem.tcp_cntrl6.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP 76411308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.gpu_tcp_st_transfers 86 # TCP to TCP store transfers 76511308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 76611680SCurtis.Dunham@arm.comsystem.tcp_cntrl6.coalescer.gpu_st_misses 20 # stores that miss in the GPU 76711308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 76811308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 76911308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 77011308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.cp_ld_misses 0 # loads that miss in the GPU 77111308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 77211308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 77311308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 77411308Santhony.gutierrez@amd.comsystem.tcp_cntrl6.coalescer.cp_st_misses 0 # stores that miss in the GPU 77511860Sandreas.hansson@arm.comsystem.tcp_cntrl6.mandatoryQueue.avg_buf_msgs 0.010201 # Average number of messages in buffer 77611860Sandreas.hansson@arm.comsystem.tcp_cntrl6.mandatoryQueue.avg_stall_time 1.122414 # Average number of cycles messages are stalled in this MB 77711860Sandreas.hansson@arm.comsystem.tcp_cntrl6.probeToTCP.avg_buf_msgs 0.009405 # Average number of messages in buffer 77811860Sandreas.hansson@arm.comsystem.tcp_cntrl6.probeToTCP.avg_stall_time 6.666763 # Average number of cycles messages are stalled in this MB 77911860Sandreas.hansson@arm.comsystem.tcp_cntrl6.requestFromTCP.avg_buf_msgs 0.335697 # Average number of messages in buffer 78011860Sandreas.hansson@arm.comsystem.tcp_cntrl6.requestFromTCP.avg_stall_time 39.618000 # Average number of cycles messages are stalled in this MB 78111860Sandreas.hansson@arm.comsystem.tcp_cntrl6.responseFromTCP.avg_buf_msgs 0.321227 # Average number of messages in buffer 78211860Sandreas.hansson@arm.comsystem.tcp_cntrl6.responseFromTCP.avg_stall_time 36.842715 # Average number of cycles messages are stalled in this MB 78311860Sandreas.hansson@arm.comsystem.tcp_cntrl6.responseToTCP.avg_buf_msgs 0.008682 # Average number of messages in buffer 78411860Sandreas.hansson@arm.comsystem.tcp_cntrl6.responseToTCP.avg_stall_time 2.959051 # Average number of cycles messages are stalled in this MB 78511680SCurtis.Dunham@arm.comsystem.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 78611860Sandreas.hansson@arm.comsystem.tcp_cntrl6.unblockFromCore.avg_buf_msgs 0.331718 # Average number of messages in buffer 78711860Sandreas.hansson@arm.comsystem.tcp_cntrl6.unblockFromCore.avg_stall_time 38.822168 # Average number of cycles messages are stalled in this MB 78811680SCurtis.Dunham@arm.comsystem.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 78911308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.L1cache.demand_hits 0 # Number of cache demand hits 79011308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.L1cache.demand_misses 0 # Number of cache demand misses 79111308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.L1cache.demand_accesses 0 # Number of cache demand accesses 79211680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.L1cache.num_data_array_reads 13 # number of data array reads 79311680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.L1cache.num_data_array_writes 101 # number of data array writes 79411680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.L1cache.num_tag_array_reads 275 # number of tag array reads 79511680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.L1cache.num_tag_array_writes 266 # number of tag array writes 79611308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.L1cache.num_tag_array_stalls 11 # number of stalls caused by tag array 79711680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 79811680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP 79911680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers 80011308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC 80111680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.coalescer.gpu_ld_misses 0 # loads that miss in the GPU 80211680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP 80311680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.coalescer.gpu_tcp_st_transfers 66 # TCP to TCP store transfers 80411308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC 80511680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.coalescer.gpu_st_misses 18 # stores that miss in the GPU 80611308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP 80711308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers 80811308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC 80911308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.coalescer.cp_ld_misses 0 # loads that miss in the GPU 81011308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP 81111308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers 81211308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC 81311308Santhony.gutierrez@amd.comsystem.tcp_cntrl7.coalescer.cp_st_misses 0 # stores that miss in the GPU 81411860Sandreas.hansson@arm.comsystem.tcp_cntrl7.mandatoryQueue.avg_buf_msgs 0.008103 # Average number of messages in buffer 81511860Sandreas.hansson@arm.comsystem.tcp_cntrl7.mandatoryQueue.avg_stall_time 1.097743 # Average number of cycles messages are stalled in this MB 81611860Sandreas.hansson@arm.comsystem.tcp_cntrl7.probeToTCP.avg_buf_msgs 0.006511 # Average number of messages in buffer 81711860Sandreas.hansson@arm.comsystem.tcp_cntrl7.probeToTCP.avg_stall_time 6.394371 # Average number of cycles messages are stalled in this MB 81811860Sandreas.hansson@arm.comsystem.tcp_cntrl7.requestFromTCP.avg_buf_msgs 0.272030 # Average number of messages in buffer 81911860Sandreas.hansson@arm.comsystem.tcp_cntrl7.requestFromTCP.avg_stall_time 39.357546 # Average number of cycles messages are stalled in this MB 82011860Sandreas.hansson@arm.comsystem.tcp_cntrl7.responseFromTCP.avg_buf_msgs 0.254739 # Average number of messages in buffer 82111860Sandreas.hansson@arm.comsystem.tcp_cntrl7.responseFromTCP.avg_stall_time 36.263927 # Average number of cycles messages are stalled in this MB 82211860Sandreas.hansson@arm.comsystem.tcp_cntrl7.responseToTCP.avg_buf_msgs 0.006801 # Average number of messages in buffer 82311860Sandreas.hansson@arm.comsystem.tcp_cntrl7.responseToTCP.avg_stall_time 2.863696 # Average number of cycles messages are stalled in this MB 82411680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 82511860Sandreas.hansson@arm.comsystem.tcp_cntrl7.unblockFromCore.avg_buf_msgs 0.269136 # Average number of messages in buffer 82611860Sandreas.hansson@arm.comsystem.tcp_cntrl7.unblockFromCore.avg_stall_time 37.901896 # Average number of cycles messages are stalled in this MB 82711680SCurtis.Dunham@arm.comsystem.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 82811308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits 82911308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses 83011308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses 83111308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.num_data_array_reads 12 # number of data array reads 83211308Santhony.gutierrez@amd.comsystem.sqc_cntrl0.L1cache.num_data_array_writes 12 # number of data array writes 83311680SCurtis.Dunham@arm.comsystem.sqc_cntrl0.L1cache.num_tag_array_reads 23 # number of tag array reads 83411680SCurtis.Dunham@arm.comsystem.sqc_cntrl0.L1cache.num_tag_array_writes 23 # number of tag array writes 83511860Sandreas.hansson@arm.comsystem.sqc_cntrl0.mandatoryQueue.avg_buf_msgs 0.000868 # Average number of messages in buffer 83611860Sandreas.hansson@arm.comsystem.sqc_cntrl0.mandatoryQueue.avg_stall_time 0.668499 # Average number of cycles messages are stalled in this MB 83711860Sandreas.hansson@arm.comsystem.sqc_cntrl0.probeToSQC.avg_buf_msgs 0.000796 # Average number of messages in buffer 83811860Sandreas.hansson@arm.comsystem.sqc_cntrl0.probeToSQC.avg_stall_time 3.344523 # Average number of cycles messages are stalled in this MB 83911860Sandreas.hansson@arm.comsystem.sqc_cntrl0.requestFromSQC.avg_buf_msgs 0.069454 # Average number of messages in buffer 84011860Sandreas.hansson@arm.comsystem.sqc_cntrl0.requestFromSQC.avg_stall_time 53.016930 # Average number of cycles messages are stalled in this MB 84111860Sandreas.hansson@arm.comsystem.sqc_cntrl0.responseFromSQC.avg_buf_msgs 0.063667 # Average number of messages in buffer 84211860Sandreas.hansson@arm.comsystem.sqc_cntrl0.responseFromSQC.avg_stall_time 37.760093 # Average number of cycles messages are stalled in this MB 84311860Sandreas.hansson@arm.comsystem.sqc_cntrl0.responseToSQC.avg_buf_msgs 0.000868 # Average number of messages in buffer 84411860Sandreas.hansson@arm.comsystem.sqc_cntrl0.responseToSQC.avg_stall_time 1.976197 # Average number of cycles messages are stalled in this MB 84511680SCurtis.Dunham@arm.comsystem.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 84611860Sandreas.hansson@arm.comsystem.sqc_cntrl0.unblockFromCore.avg_buf_msgs 0.069454 # Average number of messages in buffer 84711860Sandreas.hansson@arm.comsystem.sqc_cntrl0.unblockFromCore.avg_stall_time 52.235566 # Average number of cycles messages are stalled in this MB 84811680SCurtis.Dunham@arm.comsystem.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 84911308Santhony.gutierrez@amd.comsystem.sqc_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits 85011308Santhony.gutierrez@amd.comsystem.sqc_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses 85111308Santhony.gutierrez@amd.comsystem.sqc_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses 85211680SCurtis.Dunham@arm.comsystem.sqc_cntrl1.L1cache.num_data_array_reads 12 # number of data array reads 85311680SCurtis.Dunham@arm.comsystem.sqc_cntrl1.L1cache.num_data_array_writes 12 # number of data array writes 85411680SCurtis.Dunham@arm.comsystem.sqc_cntrl1.L1cache.num_tag_array_reads 23 # number of tag array reads 85511680SCurtis.Dunham@arm.comsystem.sqc_cntrl1.L1cache.num_tag_array_writes 23 # number of tag array writes 85611860Sandreas.hansson@arm.comsystem.sqc_cntrl1.mandatoryQueue.avg_buf_msgs 0.000868 # Average number of messages in buffer 85711860Sandreas.hansson@arm.comsystem.sqc_cntrl1.mandatoryQueue.avg_stall_time 0.585299 # Average number of cycles messages are stalled in this MB 85811860Sandreas.hansson@arm.comsystem.sqc_cntrl1.probeToSQC.avg_buf_msgs 0.000796 # Average number of messages in buffer 85911860Sandreas.hansson@arm.comsystem.sqc_cntrl1.probeToSQC.avg_stall_time 3.662060 # Average number of cycles messages are stalled in this MB 86011860Sandreas.hansson@arm.comsystem.sqc_cntrl1.requestFromSQC.avg_buf_msgs 0.069454 # Average number of messages in buffer 86111860Sandreas.hansson@arm.comsystem.sqc_cntrl1.requestFromSQC.avg_stall_time 46.360874 # Average number of cycles messages are stalled in this MB 86211860Sandreas.hansson@arm.comsystem.sqc_cntrl1.responseFromSQC.avg_buf_msgs 0.063667 # Average number of messages in buffer 86311860Sandreas.hansson@arm.comsystem.sqc_cntrl1.responseFromSQC.avg_stall_time 41.389090 # Average number of cycles messages are stalled in this MB 86411860Sandreas.hansson@arm.comsystem.sqc_cntrl1.responseToSQC.avg_buf_msgs 0.000868 # Average number of messages in buffer 86511860Sandreas.hansson@arm.comsystem.sqc_cntrl1.responseToSQC.avg_stall_time 1.726595 # Average number of cycles messages are stalled in this MB 86611680SCurtis.Dunham@arm.comsystem.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 86711860Sandreas.hansson@arm.comsystem.sqc_cntrl1.unblockFromCore.avg_buf_msgs 0.069454 # Average number of messages in buffer 86811860Sandreas.hansson@arm.comsystem.sqc_cntrl1.unblockFromCore.avg_stall_time 45.579511 # Average number of cycles messages are stalled in this MB 86911680SCurtis.Dunham@arm.comsystem.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 87011308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits 87111308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses 87211308Santhony.gutierrez@amd.comsystem.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses 87311680SCurtis.Dunham@arm.comsystem.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 87411308Santhony.gutierrez@amd.comsystem.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits 87511308Santhony.gutierrez@amd.comsystem.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses 87611308Santhony.gutierrez@amd.comsystem.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses 87711680SCurtis.Dunham@arm.comsystem.tccdir_cntrl0.directory.num_tag_array_reads 896 # number of tag array reads 87811680SCurtis.Dunham@arm.comsystem.tccdir_cntrl0.directory.num_tag_array_writes 882 # number of tag array writes 87911860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.probeFromNB.avg_buf_msgs 0.035740 # Average number of messages in buffer 88011860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.probeFromNB.avg_stall_time 35.754884 # Average number of cycles messages are stalled in this MB 88111860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.probeToCore.avg_buf_msgs 0.265157 # Average number of messages in buffer 88211860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.probeToCore.avg_stall_time 4.884604 # Average number of cycles messages are stalled in this MB 88311860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.requestFromTCP.avg_buf_msgs 1.395239 # Average number of messages in buffer 88411860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.requestFromTCP.avg_stall_time 55.396180 # Average number of cycles messages are stalled in this MB 88511860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.requestToNB.avg_buf_msgs 1.900159 # Average number of messages in buffer 88611860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.requestToNB.avg_stall_time 118.576183 # Average number of cycles messages are stalled in this MB 88711860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.responseFromNB.avg_buf_msgs 0.015627 # Average number of messages in buffer 88811860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.responseFromNB.avg_stall_time 33.355520 # Average number of cycles messages are stalled in this MB 88911860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.responseFromTCP.avg_buf_msgs 0.056794 # Average number of messages in buffer 89011860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.responseFromTCP.avg_stall_time 41.713066 # Average number of cycles messages are stalled in this MB 89111860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.responseToCore.avg_buf_msgs 0.058602 # Average number of messages in buffer 89211860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.responseToCore.avg_stall_time 0.980972 # Average number of cycles messages are stalled in this MB 89311860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.responseToNB.avg_buf_msgs 0.718203 # Average number of messages in buffer 89411860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.responseToNB.avg_stall_time 117.951092 # Average number of cycles messages are stalled in this MB 89511860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.triggerQueue.avg_buf_msgs 0.052814 # Average number of messages in buffer 89611860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.triggerQueue.avg_stall_time 0.973665 # Average number of cycles messages are stalled in this MB 89711860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.unblockFromTCP.avg_buf_msgs 0.058602 # Average number of messages in buffer 89811860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.unblockFromTCP.avg_stall_time 42.100275 # Average number of cycles messages are stalled in this MB 89911860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.unblockToNB.avg_buf_msgs 1.864274 # Average number of messages in buffer 90011860Sandreas.hansson@arm.comsystem.tccdir_cntrl0.unblockToNB.avg_stall_time 116.292866 # Average number of cycles messages are stalled in this MB 90111680SCurtis.Dunham@arm.comsystem.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 90211860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers00.avg_buf_msgs 0.015627 # Average number of messages in buffer 90311860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers00.avg_stall_time 31.536970 # Average number of cycles messages are stalled in this MB 90411860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers02.avg_buf_msgs 0.011069 # Average number of messages in buffer 90511860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers02.avg_stall_time 12.697222 # Average number of cycles messages are stalled in this MB 90611860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers10.avg_buf_msgs 0.006077 # Average number of messages in buffer 90711860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers10.avg_stall_time 31.736073 # Average number of cycles messages are stalled in this MB 90811860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers12.avg_buf_msgs 0.015627 # Average number of messages in buffer 90911860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers12.avg_stall_time 31.398061 # Average number of cycles messages are stalled in this MB 91011860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers20.avg_buf_msgs 0.011214 # Average number of messages in buffer 91111860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers20.avg_stall_time 16.901606 # Average number of cycles messages are stalled in this MB 91211860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers22.avg_buf_msgs 0.020764 # Average number of messages in buffer 91311860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers22.avg_stall_time 16.730647 # Average number of cycles messages are stalled in this MB 91411860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers24.avg_buf_msgs 0.005860 # Average number of messages in buffer 91511860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers24.avg_stall_time 16.583056 # Average number of cycles messages are stalled in this MB 91611860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers30.avg_buf_msgs 0.015700 # Average number of messages in buffer 91711860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers30.avg_stall_time 120.534800 # Average number of cycles messages are stalled in this MB 91811860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers32.avg_buf_msgs 0.005933 # Average number of messages in buffer 91911860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers32.avg_stall_time 119.899291 # Average number of cycles messages are stalled in this MB 92011860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers34.avg_buf_msgs 0.015483 # Average number of messages in buffer 92111860Sandreas.hansson@arm.comsystem.ruby.network.int_link_buffers34.avg_stall_time 118.213428 # Average number of cycles messages are stalled in this MB 92211680SCurtis.Dunham@arm.comsystem.ruby.network.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 92311680SCurtis.Dunham@arm.comsystem.ruby.network.msg_count.Control 1389 92411680SCurtis.Dunham@arm.comsystem.ruby.network.msg_count.Request_Control 1567 92511680SCurtis.Dunham@arm.comsystem.ruby.network.msg_count.Response_Data 2360 92611680SCurtis.Dunham@arm.comsystem.ruby.network.msg_count.Response_Control 436 92711680SCurtis.Dunham@arm.comsystem.ruby.network.msg_count.Writeback_Data 134 92811680SCurtis.Dunham@arm.comsystem.ruby.network.msg_count.Writeback_Control 142 92911680SCurtis.Dunham@arm.comsystem.ruby.network.msg_count.Unblock_Control 1400 93011680SCurtis.Dunham@arm.comsystem.ruby.network.msg_byte.Control 11112 93111680SCurtis.Dunham@arm.comsystem.ruby.network.msg_byte.Request_Control 12536 93211680SCurtis.Dunham@arm.comsystem.ruby.network.msg_byte.Response_Data 169920 93311680SCurtis.Dunham@arm.comsystem.ruby.network.msg_byte.Response_Control 3488 93411680SCurtis.Dunham@arm.comsystem.ruby.network.msg_byte.Writeback_Data 9648 93511680SCurtis.Dunham@arm.comsystem.ruby.network.msg_byte.Writeback_Control 1136 93611680SCurtis.Dunham@arm.comsystem.ruby.network.msg_byte.Unblock_Control 11200 93711680SCurtis.Dunham@arm.comsystem.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states 93811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle0.link_utilization 0.254594 93911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0 372 94011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Data::2 85 94111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Control::2 217 94211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle0.msg_count.Writeback_Data::2 67 94311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle0.msg_count.Unblock_Control::4 295 94411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Request_Control::0 2976 94511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Data::2 6120 94611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Control::2 1736 94711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Writeback_Data::2 4824 94811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Unblock_Control::4 2360 94911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle1.link_utilization 0.115879 95011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle1.msg_count.Control::0 216 95111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle1.msg_count.Response_Data::2 82 95211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle1.msg_count.Writeback_Control::2 71 95311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Control::0 1728 95411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Response_Data::2 5904 95511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Writeback_Control::2 568 95611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle2.link_utilization 0.229271 95711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle2.msg_count.Control::0 84 95811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle2.msg_count.Response_Data::2 216 95911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Control::0 672 96011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Response_Data::2 15552 96111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle0.link_utilization 0.115879 96211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle0.msg_count.Control::0 216 96311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle0.msg_count.Response_Data::2 82 96411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle0.msg_count.Writeback_Control::2 71 96511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Control::0 1728 96611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Response_Data::2 5904 96711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Writeback_Control::2 568 96811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle1.link_utilization 0.131480 96911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle1.msg_count.Request_Control::0 155 97011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Data::2 13 97111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Control::2 207 97211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle1.msg_count.Writeback_Data::2 67 97311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle1.msg_count.Unblock_Control::4 81 97411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Request_Control::0 1240 97511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Data::2 936 97611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Control::2 1656 97711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Writeback_Data::2 4824 97811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Unblock_Control::4 648 97911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle0.link_utilization 0.116105 98011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle0.msg_count.Control::1 100 98111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle0.msg_count.Response_Data::3 103 98211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Control::1 800 98311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Response_Data::3 7416 98411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle1.link_utilization 0.109661 98511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle1.msg_count.Control::1 97 98611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle1.msg_count.Response_Data::3 97 98711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Control::1 776 98811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Response_Data::3 6984 98911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle2.link_utilization 0.108078 99011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle2.msg_count.Control::1 92 99111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle2.msg_count.Response_Data::3 96 99211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Control::1 736 99311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Response_Data::3 6912 99411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle3.link_utilization 0.099260 99511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.throttle3.msg_count.Control::1 86 99611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle3.msg_count.Response_Data::3 88 99711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Control::1 688 99811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Response_Data::3 6336 99911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle4.link_utilization 0.116557 100011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.throttle4.msg_count.Control::1 104 100111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle4.msg_count.Response_Data::3 103 100211308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Control::1 832 100311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Response_Data::3 7416 100411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle5.link_utilization 0.103556 100511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle5.msg_count.Control::1 88 100611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle5.msg_count.Response_Data::3 92 100711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Control::1 704 100811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Response_Data::3 6624 100911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle6.link_utilization 0.129558 101011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle6.msg_count.Control::1 111 101111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle6.msg_count.Response_Data::3 115 101211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Control::1 888 101311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Response_Data::3 8280 101411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle7.link_utilization 0.104687 101511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle7.msg_count.Control::1 89 101611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle7.msg_count.Response_Data::3 93 101711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Control::1 712 101811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Response_Data::3 6696 101911308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.throttle8.link_utilization 0 102011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle9.link_utilization 1.210793 102111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_count.Control::0 84 102211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_count.Request_Control::1 823 102311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::2 216 102411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::3 783 102511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Control::3 2 102611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_count.Unblock_Control::5 810 102711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Control::0 672 102811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Request_Control::1 6584 102911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::2 15552 103011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::3 56376 103111308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Control::3 16 103211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Unblock_Control::5 6480 103311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle10.link_utilization 0.013453 103411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle10.msg_count.Control::1 11 103511308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.throttle10.msg_count.Response_Data::3 12 103611680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Control::1 88 103711308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Response_Data::3 864 103811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle11.link_utilization 0.013453 103911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle11.msg_count.Control::1 11 104011680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle11.msg_count.Response_Data::3 12 104111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Control::1 88 104211680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Response_Data::3 864 104311680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle12.link_utilization 0.123114 104411680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle12.msg_count.Request_Control::0 217 104511680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Data::2 72 104611308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Control::2 10 104711680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle12.msg_count.Unblock_Control::4 214 104811680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Request_Control::0 1736 104911680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Data::2 5184 105011308Santhony.gutierrez@amd.comsystem.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Control::2 80 105111680SCurtis.Dunham@arm.comsystem.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Unblock_Control::4 1712 105211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Load_L1miss 1 0.00% 0.00% 105311680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.C1_Load_L1miss 2 0.00% 0.00% 105411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Ifetch0_L1miss 2 0.00% 0.00% 105511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.Ifetch1_L1miss 1 0.00% 0.00% 105611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Store_L1miss 45 0.00% 0.00% 105711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.C0_Store_L1hit 2 0.00% 0.00% 105811680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.C1_Store_L1miss 72 0.00% 0.00% 105911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.NB_AckS 4 0.00% 0.00% 106011680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.NB_AckM 78 0.00% 0.00% 106111680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.NB_AckWB 71 0.00% 0.00% 106211680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.L1D0_Repl 11 0.00% 0.00% 106311680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.L2_Repl 35555 0.00% 0.00% 106411680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.PrbInvData 212 0.00% 0.00% 106511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.PrbShrData 4 0.00% 0.00% 106611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.C0_Load_L1miss 1 0.00% 0.00% 106711680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.I.C1_Load_L1miss 2 0.00% 0.00% 106811308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.Ifetch0_L1miss 2 0.00% 0.00% 106911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.Ifetch1_L1miss 1 0.00% 0.00% 107011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I.C0_Store_L1miss 41 0.00% 0.00% 107111680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.I.C1_Store_L1miss 38 0.00% 0.00% 107211680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.I.PrbInvData 198 0.00% 0.00% 107311680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.I.PrbShrData 4 0.00% 0.00% 107411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.L2_Repl 3 0.00% 0.00% 107511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S.PrbInvData 1 0.00% 0.00% 107611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.C0_Store_L1hit 2 0.00% 0.00% 107711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M0.L2_Repl 33 0.00% 0.00% 107811680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.M0.PrbInvData 6 0.00% 0.00% 107911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M1.C0_Store_L1miss 1 0.00% 0.00% 108011308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.M1.L2_Repl 36 0.00% 0.00% 108111680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.M1.PrbInvData 3 0.00% 0.00% 108211308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_M0.C1_Store_L1miss 5 0.00% 0.00% 108311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_M0.NB_AckM 35 0.00% 0.00% 108411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_M0.L1D0_Repl 11 0.00% 0.00% 108511680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.I_M0.L2_Repl 15350 0.00% 0.00% 108611308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_M1.C0_Store_L1miss 3 0.00% 0.00% 108711680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.I_M1.NB_AckM 35 0.00% 0.00% 108811680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.I_M1.L2_Repl 14410 0.00% 0.00% 108911308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_M0M1.NB_AckM 5 0.00% 0.00% 109011680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.I_M0M1.L2_Repl 3283 0.00% 0.00% 109111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_M1M0.NB_AckM 3 0.00% 0.00% 109211680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.I_M1M0.L2_Repl 1200 0.00% 0.00% 109311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_E0S.NB_AckS 1 0.00% 0.00% 109411680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.I_E0S.L2_Repl 404 0.00% 0.00% 109511308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_E1S.NB_AckS 1 0.00% 0.00% 109611680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.I_E1S.L2_Repl 392 0.00% 0.00% 109711308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.ES_I.NB_AckWB 2 0.00% 0.00% 109811680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.MO_I.NB_AckWB 65 0.00% 0.00% 109911680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.MO_I.PrbInvData 4 0.00% 0.00% 110011680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.S0.C1_Store_L1miss 29 0.00% 0.00% 110111308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S0.NB_AckS 1 0.00% 0.00% 110211680SCurtis.Dunham@arm.comsystem.ruby.CorePair_Controller.S0.L2_Repl 444 0.00% 0.00% 110311308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.S1.NB_AckS 1 0.00% 0.00% 110411308Santhony.gutierrez@amd.comsystem.ruby.CorePair_Controller.I_C.NB_AckWB 4 0.00% 0.00% 110511680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.RdBlkS 4 0.00% 0.00% 110611680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.RdBlkM 297 0.00% 0.00% 110711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.RdBlk 6 0.00% 0.00% 110811680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.VicDirty 69 0.00% 0.00% 110911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.VicClean 2 0.00% 0.00% 111011680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.CPUData 67 0.00% 0.00% 111111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.StaleWB 4 0.00% 0.00% 111211680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.CPUPrbResp 298 0.00% 0.00% 111311680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.ProbeAcksComplete 298 0.00% 0.00% 111411680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.L3Hit 45 0.00% 0.00% 111511680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.MemData 256 0.00% 0.00% 111611680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.WBAck 14 0.00% 0.00% 111711680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.CoreUnblock 295 0.00% 0.00% 111811680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.U.RdBlkS 4 0.00% 0.00% 111911680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.U.RdBlkM 291 0.00% 0.00% 112011680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.U.RdBlk 6 0.00% 0.00% 112111680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.U.VicDirty 69 0.00% 0.00% 112211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.U.VicClean 2 0.00% 0.00% 112311680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.U.WBAck 14 0.00% 0.00% 112411680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.BL.CPUData 67 0.00% 0.00% 112511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BL.StaleWB 4 0.00% 0.00% 112611680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.BM_M.MemData 9 0.00% 0.00% 112711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_PM.L3Hit 1 0.00% 0.00% 112811680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.BS_PM.MemData 3 0.00% 0.00% 112911308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_PM.RdBlkM 1 0.00% 0.00% 113011680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.BM_PM.CPUPrbResp 13 0.00% 0.00% 113111680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 9 0.00% 0.00% 113211680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.BM_PM.L3Hit 41 0.00% 0.00% 113311680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.BM_PM.MemData 241 0.00% 0.00% 113411680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.B_PM.L3Hit 3 0.00% 0.00% 113511308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_PM.MemData 3 0.00% 0.00% 113611308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_Pm.CPUPrbResp 3 0.00% 0.00% 113711308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 3 0.00% 0.00% 113811308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.BM_Pm.RdBlkM 3 0.00% 0.00% 113911680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.BM_Pm.CPUPrbResp 277 0.00% 0.00% 114011680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 281 0.00% 0.00% 114111308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_Pm.CPUPrbResp 5 0.00% 0.00% 114211308Santhony.gutierrez@amd.comsystem.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 5 0.00% 0.00% 114311680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.B.RdBlkM 2 0.00% 0.00% 114411680SCurtis.Dunham@arm.comsystem.ruby.Directory_Controller.B.CoreUnblock 295 0.00% 0.00% 114511312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::bucket_size 1024 114611312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::max_bucket 10239 114711312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::samples 1 114811680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::mean 5256 114911680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::gmean 5256.000000 115011312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::stdev nan 115111312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 115211312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::total 1 115311680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_coalsr::bucket_size 64 115411680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_coalsr::max_bucket 639 115511680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_coalsr::samples 72 115611680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_coalsr::mean 101.402778 115711680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_coalsr::gmean 68.071118 115811680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_coalsr::stdev 67.272969 115911680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_coalsr | 7 9.72% 9.72% | 60 83.33% 93.06% | 1 1.39% 94.44% | 0 0.00% 94.44% | 3 4.17% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 116011680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_coalsr::total 72 116111312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::bucket_size 1024 116211312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::max_bucket 10239 116311312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::samples 1 116411680SCurtis.Dunham@arm.comsystem.ruby.LD.hit_latency_hist_seqr::mean 5256 116511680SCurtis.Dunham@arm.comsystem.ruby.LD.hit_latency_hist_seqr::gmean 5256.000000 116611312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::stdev nan 116711312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 116811312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::total 1 116911680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 117011680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 117111680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_coalsr::samples 72 117211680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_coalsr::mean 101.402778 117311680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_coalsr::gmean 68.071118 117411680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_coalsr::stdev 67.272969 117511680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_coalsr | 7 9.72% 9.72% | 60 83.33% 93.06% | 1 1.39% 94.44% | 0 0.00% 94.44% | 3 4.17% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 117611680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_coalsr::total 72 117711312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::bucket_size 1024 117811312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::max_bucket 10239 117911312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::samples 46 118011680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::mean 3234.260870 118111680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::gmean 1760.149244 118211680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::stdev 1907.255858 118311680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr | 11 23.91% 23.91% | 3 6.52% 30.43% | 3 6.52% 36.96% | 7 15.22% 52.17% | 20 43.48% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 118411312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::total 46 118511312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr::bucket_size 128 118611312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_coalsr::max_bucket 1279 118711680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_coalsr::samples 786 118811680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_coalsr::mean 225.797710 118911680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_coalsr::gmean 112.544056 119011680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_coalsr::stdev 244.652456 119111680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_coalsr | 506 64.38% 64.38% | 35 4.45% 68.83% | 108 13.74% 82.57% | 36 4.58% 87.15% | 24 3.05% 90.20% | 19 2.42% 92.62% | 32 4.07% 96.69% | 23 2.93% 99.62% | 3 0.38% 100.00% | 0 0.00% 100.00% 119211680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_coalsr::total 786 119311312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::bucket_size 1024 119411312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::max_bucket 10239 119511312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::samples 40 119611680SCurtis.Dunham@arm.comsystem.ruby.ST.hit_latency_hist_seqr::mean 3566.725000 119711680SCurtis.Dunham@arm.comsystem.ruby.ST.hit_latency_hist_seqr::gmean 2651.630943 119811680SCurtis.Dunham@arm.comsystem.ruby.ST.hit_latency_hist_seqr::stdev 1765.919997 119911680SCurtis.Dunham@arm.comsystem.ruby.ST.hit_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 20 50.00% 95.00% | 2 5.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 120011312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::total 40 120111312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::bucket_size 512 120211312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::max_bucket 5119 120311312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::samples 6 120411680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::mean 1017.833333 120511680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::gmean 114.584426 120611680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::stdev 1278.753677 120711680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 120811312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::total 6 120911312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr::bucket_size 128 121011312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_coalsr::max_bucket 1279 121111680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_coalsr::samples 786 121211680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_coalsr::mean 225.797710 121311680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_coalsr::gmean 112.544056 121411680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_coalsr::stdev 244.652456 121511680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_coalsr | 506 64.38% 64.38% | 35 4.45% 68.83% | 108 13.74% 82.57% | 36 4.58% 87.15% | 24 3.05% 90.20% | 19 2.42% 92.62% | 32 4.07% 96.69% | 23 2.93% 99.62% | 3 0.38% 100.00% | 0 0.00% 100.00% 121611680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_coalsr::total 786 121711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::bucket_size 1024 121811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::max_bucket 10239 121911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::samples 1 122011680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::mean 5129 122111680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::gmean 5129 122211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::stdev nan 122311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 122411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::total 1 122511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1024 122611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 10239 122711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::samples 1 122811680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.hit_latency_hist_seqr::mean 5129 122911680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.hit_latency_hist_seqr::gmean 5129 123011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::stdev nan 123111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 123211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::total 1 123311312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 512 123411312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 5119 123511312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 6 123611680SCurtis.Dunham@arm.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 1017.833333 123711680SCurtis.Dunham@arm.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 114.584426 123811680SCurtis.Dunham@arm.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 1278.753677 123911680SCurtis.Dunham@arm.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 124011312Santhony.gutierrez@amd.comsystem.ruby.L1Cache.miss_mach_latency_hist_seqr::total 6 124111312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 1024 124211312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 10239 124311312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::samples 42 124411680SCurtis.Dunham@arm.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::mean 3644.142857 124511680SCurtis.Dunham@arm.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::gmean 2737.850881 124611680SCurtis.Dunham@arm.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::stdev 1757.652877 124711680SCurtis.Dunham@arm.comsystem.ruby.Directory.hit_mach_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 20 47.62% 90.48% | 4 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 124811312Santhony.gutierrez@amd.comsystem.ruby.Directory.hit_mach_latency_hist_seqr::total 42 124911312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 128 125011312Santhony.gutierrez@amd.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 1279 125111680SCurtis.Dunham@arm.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 624 125211680SCurtis.Dunham@arm.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 148.483974 125311680SCurtis.Dunham@arm.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 122.381501 125411680SCurtis.Dunham@arm.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 128.958613 125511680SCurtis.Dunham@arm.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 502 80.45% 80.45% | 36 5.77% 86.22% | 40 6.41% 92.63% | 24 3.85% 96.47% | 12 1.92% 98.40% | 6 0.96% 99.36% | 3 0.48% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 125611680SCurtis.Dunham@arm.comsystem.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 624 125711312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 125811312Santhony.gutierrez@amd.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 125911680SCurtis.Dunham@arm.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::samples 71 126011680SCurtis.Dunham@arm.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.126761 126111680SCurtis.Dunham@arm.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.060325 126211680SCurtis.Dunham@arm.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.607796 126311680SCurtis.Dunham@arm.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 68 95.77% 95.77% | 0 0.00% 95.77% | 0 0.00% 95.77% | 3 4.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 126411680SCurtis.Dunham@arm.comsystem.ruby.TCP.miss_mach_latency_hist_coalsr::total 71 126511312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 128 126611312Santhony.gutierrez@amd.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 1279 126711680SCurtis.Dunham@arm.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 163 126811680SCurtis.Dunham@arm.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 564.687117 126911680SCurtis.Dunham@arm.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 498.870659 127011680SCurtis.Dunham@arm.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 272.472640 127111680SCurtis.Dunham@arm.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 71 43.56% 43.56% | 13 7.98% 51.53% | 12 7.36% 58.90% | 13 7.98% 66.87% | 29 17.79% 84.66% | 22 13.50% 98.16% | 3 1.84% 100.00% | 0 0.00% 100.00% 127211680SCurtis.Dunham@arm.comsystem.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 163 127311312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 127411312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 127511312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 1 127611680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 5256 127711680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 5256.000000 127811312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev nan 127911312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 128011312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 1 128111680SCurtis.Dunham@arm.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 128211680SCurtis.Dunham@arm.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 128311312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 62 128411680SCurtis.Dunham@arm.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 104.322581 128511680SCurtis.Dunham@arm.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 100.218451 128611680SCurtis.Dunham@arm.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 51.260433 128711680SCurtis.Dunham@arm.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 60 96.77% 96.77% | 1 1.61% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 1 1.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 128811312Santhony.gutierrez@amd.comsystem.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 62 128911312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 129011312Santhony.gutierrez@amd.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 129111680SCurtis.Dunham@arm.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 7 129211680SCurtis.Dunham@arm.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 1.428571 129311680SCurtis.Dunham@arm.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.219014 129411680SCurtis.Dunham@arm.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 1.133893 129511680SCurtis.Dunham@arm.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 6 85.71% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 129611680SCurtis.Dunham@arm.comsystem.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 7 129711680SCurtis.Dunham@arm.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 129811680SCurtis.Dunham@arm.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 129911312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 3 130011680SCurtis.Dunham@arm.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 274.333333 130111680SCurtis.Dunham@arm.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273.844265 130211680SCurtis.Dunham@arm.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 20.256686 130311680SCurtis.Dunham@arm.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 1 33.33% 100.00% 130411312Santhony.gutierrez@amd.comsystem.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 3 130511312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512 130611312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119 130711312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 6 130811680SCurtis.Dunham@arm.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1017.833333 130911680SCurtis.Dunham@arm.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 114.584426 131011680SCurtis.Dunham@arm.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 1278.753677 131111680SCurtis.Dunham@arm.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 131211312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 6 131311312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 131411312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 131511312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 40 131611680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 3566.725000 131711680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 2651.630943 131811680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 1765.919997 131911680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 20 50.00% 95.00% | 2 5.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 132011312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 40 132111312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 128 132211312Santhony.gutierrez@amd.comsystem.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 1279 132311680SCurtis.Dunham@arm.comsystem.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 562 132411680SCurtis.Dunham@arm.comsystem.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 153.355872 132511680SCurtis.Dunham@arm.comsystem.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 125.108856 132611680SCurtis.Dunham@arm.comsystem.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 133.952348 132711680SCurtis.Dunham@arm.comsystem.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 442 78.65% 78.65% | 35 6.23% 84.88% | 40 7.12% 91.99% | 23 4.09% 96.09% | 12 2.14% 98.22% | 6 1.07% 99.29% | 3 0.53% 99.82% | 1 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 132811680SCurtis.Dunham@arm.comsystem.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 562 132911312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 133011312Santhony.gutierrez@amd.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 133111680SCurtis.Dunham@arm.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 64 133211680SCurtis.Dunham@arm.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1.093750 133311680SCurtis.Dunham@arm.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.044274 133411680SCurtis.Dunham@arm.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.526104 133511680SCurtis.Dunham@arm.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 62 96.88% 96.88% | 0 0.00% 96.88% | 0 0.00% 96.88% | 2 3.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 133611680SCurtis.Dunham@arm.comsystem.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 64 133711312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 128 133811312Santhony.gutierrez@amd.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 1279 133911680SCurtis.Dunham@arm.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 160 134011680SCurtis.Dunham@arm.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 570.131250 134111680SCurtis.Dunham@arm.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 504.512629 134211680SCurtis.Dunham@arm.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 272.059675 134311680SCurtis.Dunham@arm.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 68 42.50% 42.50% | 13 8.12% 50.62% | 12 7.50% 58.12% | 13 8.12% 66.25% | 29 18.12% 84.38% | 22 13.75% 98.12% | 3 1.88% 100.00% | 0 0.00% 100.00% 134411680SCurtis.Dunham@arm.comsystem.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 160 134511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 134611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 134711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1 134811680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 5129 134911680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 5129 135011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev nan 135111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 135211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1 135311680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.Fetch | 12 50.00% 50.00% | 12 50.00% 100.00% 135411680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.Fetch::total 24 135511680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.TCC_AckS | 12 50.00% 50.00% | 12 50.00% 100.00% 135611680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.TCC_AckS::total 24 135711680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.PrbInvData | 11 50.00% 50.00% | 11 50.00% 100.00% 135811680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.PrbInvData::total 22 135911680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.I.Fetch | 12 50.00% 50.00% | 12 50.00% 100.00% 136011680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.I.Fetch::total 24 136111680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.S.PrbInvData | 11 50.00% 50.00% | 11 50.00% 100.00% 136211680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.S.PrbInvData::total 22 136311680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.I_S.TCC_AckS | 12 50.00% 50.00% | 12 50.00% 100.00% 136411680SCurtis.Dunham@arm.comsystem.ruby.SQC_Controller.I_S.TCC_AckS::total 24 136511680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.RdBlk 115 0.00% 0.00% 136611680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.RdBlkM 2448 0.00% 0.00% 136711680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.RdBlkS 103 0.00% 0.00% 136811680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.CPUPrbResp 785 0.00% 0.00% 136911680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.ProbeAcksComplete 730 0.00% 0.00% 137011680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.CoreUnblock 807 0.00% 0.00% 137111680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.LastCoreUnblock 3 0.00% 0.00% 137211680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.NB_AckS 1 0.00% 0.00% 137311680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.NB_AckE 3 0.00% 0.00% 137411680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.NB_AckM 212 0.00% 0.00% 137511680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.PrbInvData 119 0.00% 0.00% 137611680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.PrbShrData 6 0.00% 0.00% 137711308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.RdBlk 3 0.00% 0.00% 137811680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.I.RdBlkM 154 0.00% 0.00% 137911308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.RdBlkS 1 0.00% 0.00% 138011308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I.PrbInvData 9 0.00% 0.00% 138111680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.S.RdBlkM 1 0.00% 0.00% 138211308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.E.RdBlkM 1 0.00% 0.00% 138311680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.E.RdBlkS 1 0.00% 0.00% 138411680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.O.RdBlk 2 0.00% 0.00% 138511680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.O.RdBlkM 61 0.00% 0.00% 138611680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.O.RdBlkS 1 0.00% 0.00% 138711680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.O.PrbInvData 4 0.00% 0.00% 138811680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.O.PrbShrData 1 0.00% 0.00% 138911308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.M.RdBlk 61 0.00% 0.00% 139011680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.M.RdBlkM 512 0.00% 0.00% 139111680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.M.RdBlkS 20 0.00% 0.00% 139211680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.M.PrbInvData 62 0.00% 0.00% 139311308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.M.PrbShrData 4 0.00% 0.00% 139411680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.CP_I.RdBlkM 17 0.00% 0.00% 139511680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.CP_I.CPUPrbResp 70 0.00% 0.00% 139611680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 66 0.00% 0.00% 139711308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_O.RdBlkM 4 0.00% 0.00% 139811680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.CP_O.CPUPrbResp 6 0.00% 0.00% 139911680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 5 0.00% 0.00% 140011680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.CP_OM.RdBlkM 14 0.00% 0.00% 140111680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.CP_OM.CPUPrbResp 1 0.00% 0.00% 140211680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.CP_OM.ProbeAcksComplete 1 0.00% 0.00% 140311308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_IOM.RdBlkM 5 0.00% 0.00% 140411308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_IOM.CPUPrbResp 2 0.00% 0.00% 140511308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.CP_IOM.ProbeAcksComplete 2 0.00% 0.00% 140611680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.I_M.RdBlk 26 0.00% 0.00% 140711680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.I_M.RdBlkM 960 0.00% 0.00% 140811680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.I_M.RdBlkS 3 0.00% 0.00% 140911680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.I_M.NB_AckM 154 0.00% 0.00% 141011308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I_M.PrbInvData 1 0.00% 0.00% 141111680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.I_ES.NB_AckE 3 0.00% 0.00% 141211308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.I_S.NB_AckS 1 0.00% 0.00% 141311680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBO_O.RdBlkM 5 0.00% 0.00% 141411680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBO_O.RdBlkS 1 0.00% 0.00% 141511680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBO_O.CPUPrbResp 3 0.00% 0.00% 141611680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBO_O.ProbeAcksComplete 3 0.00% 0.00% 141711680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBM_M.RdBlk 6 0.00% 0.00% 141811680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBM_M.RdBlkM 94 0.00% 0.00% 141911680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBM_M.RdBlkS 5 0.00% 0.00% 142011680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 510 0.00% 0.00% 142111680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 510 0.00% 0.00% 142211680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBM_M.PrbInvData 15 0.00% 0.00% 142311680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBM_O.RdBlkM 6 0.00% 0.00% 142411680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBM_O.RdBlkS 5 0.00% 0.00% 142511680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBM_O.CPUPrbResp 81 0.00% 0.00% 142611680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBM_O.ProbeAcksComplete 81 0.00% 0.00% 142711680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BB_M.RdBlk 13 0.00% 0.00% 142811680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BB_M.RdBlkM 176 0.00% 0.00% 142911680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BB_M.RdBlkS 5 0.00% 0.00% 143011680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BB_M.CoreUnblock 509 0.00% 0.00% 143111680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BB_M.PrbInvData 24 0.00% 0.00% 143211680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BB_O.RdBlkM 26 0.00% 0.00% 143311680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BB_O.RdBlkS 5 0.00% 0.00% 143411680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BB_O.CoreUnblock 81 0.00% 0.00% 143511308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.BB_O.PrbInvData 2 0.00% 0.00% 143611680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BB_OO.RdBlkM 14 0.00% 0.00% 143711680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BB_OO.CoreUnblock 1 0.00% 0.00% 143811680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BB_OO.LastCoreUnblock 3 0.00% 0.00% 143911680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBS_M.CPUPrbResp 2 0.00% 0.00% 144011680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBS_M.ProbeAcksComplete 2 0.00% 0.00% 144111680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBO_M.RdBlkM 4 0.00% 0.00% 144211680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBO_M.CPUPrbResp 110 0.00% 0.00% 144311680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBO_M.ProbeAcksComplete 60 0.00% 0.00% 144411680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.S_M.NB_AckM 2 0.00% 0.00% 144511680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.O_M.RdBlkM 198 0.00% 0.00% 144611680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.O_M.RdBlkS 48 0.00% 0.00% 144711680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.O_M.NB_AckM 56 0.00% 0.00% 144811308Santhony.gutierrez@amd.comsystem.ruby.TCCdir_Controller.O_M.PrbInvData 2 0.00% 0.00% 144911680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.O_M.PrbShrData 1 0.00% 0.00% 145011680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBB_S.CoreUnblock 1 0.00% 0.00% 145111680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBB_M.RdBlk 4 0.00% 0.00% 145211680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBB_M.RdBlkM 196 0.00% 0.00% 145311680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBB_M.RdBlkS 8 0.00% 0.00% 145411680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBB_M.CoreUnblock 212 0.00% 0.00% 145511680SCurtis.Dunham@arm.comsystem.ruby.TCCdir_Controller.BBB_E.CoreUnblock 3 0.00% 0.00% 145611680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.Load | 10 13.70% 13.70% | 10 13.70% 27.40% | 11 15.07% 42.47% | 12 16.44% 58.90% | 6 8.22% 67.12% | 3 4.11% 71.23% | 10 13.70% 84.93% | 11 15.07% 100.00% 145711680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.Load::total 73 145811680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.Store | 106 13.27% 13.27% | 102 12.77% 26.03% | 97 12.14% 38.17% | 86 10.76% 48.94% | 107 13.39% 62.33% | 98 12.27% 74.59% | 111 13.89% 88.49% | 92 11.51% 100.00% 145911680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.Store::total 799 146011680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.TCC_AckS | 9 14.52% 14.52% | 8 12.90% 27.42% | 8 12.90% 40.32% | 12 19.35% 59.68% | 5 8.06% 67.74% | 3 4.84% 72.58% | 8 12.90% 85.48% | 9 14.52% 100.00% 146111680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.TCC_AckS::total 62 146211680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.TCC_AckE | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% 146311680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.TCC_AckE::total 3 146411680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.TCC_AckM | 93 12.88% 12.88% | 89 12.33% 25.21% | 87 12.05% 37.26% | 76 10.53% 47.78% | 98 13.57% 61.36% | 89 12.33% 73.68% | 106 14.68% 88.37% | 84 11.63% 100.00% 146511680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.TCC_AckM::total 722 146611680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.PrbInvData | 84 12.44% 12.44% | 87 12.89% 25.33% | 83 12.30% 37.63% | 78 11.56% 49.19% | 89 13.19% 62.37% | 79 11.70% 74.07% | 97 14.37% 88.44% | 78 11.56% 100.00% 146711680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.PrbInvData::total 675 146811680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.PrbShrData | 16 17.39% 17.39% | 10 10.87% 28.26% | 9 9.78% 38.04% | 8 8.70% 46.74% | 15 16.30% 63.04% | 9 9.78% 72.83% | 14 15.22% 88.04% | 11 11.96% 100.00% 146911308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.PrbShrData::total 92 147011680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.I.Load | 10 15.15% 15.15% | 9 13.64% 28.79% | 9 13.64% 42.42% | 12 18.18% 60.61% | 5 7.58% 68.18% | 3 4.55% 72.73% | 9 13.64% 86.36% | 9 13.64% 100.00% 147111680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.I.Load::total 66 147211680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.I.Store | 97 13.42% 13.42% | 91 12.59% 26.00% | 87 12.03% 38.04% | 79 10.93% 48.96% | 92 12.72% 61.69% | 89 12.31% 74.00% | 104 14.38% 88.38% | 84 11.62% 100.00% 147311680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.I.Store::total 723 147411308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 147511308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.I.PrbInvData::total 2 147611680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% 147711680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.S.Store::total 3 147811680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.S.PrbInvData | 6 14.29% 14.29% | 7 16.67% 30.95% | 7 16.67% 47.62% | 7 16.67% 64.29% | 2 4.76% 69.05% | 1 2.38% 71.43% | 5 11.90% 83.33% | 7 16.67% 100.00% 147911680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.S.PrbInvData::total 42 148011680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.S.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 148111308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.S.PrbShrData::total 1 148211308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.E.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 148311308Santhony.gutierrez@amd.comsystem.ruby.TCP_Controller.E.PrbInvData::total 1 148411680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.E.PrbShrData | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 148511680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.E.PrbShrData::total 1 148611680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.O.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 11.11% 11.11% | 0 0.00% 11.11% | 5 55.56% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00% 148711680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.O.Store::total 9 148811680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.O.PrbInvData | 9 16.07% 16.07% | 7 12.50% 28.57% | 8 14.29% 42.86% | 8 14.29% 57.14% | 7 12.50% 69.64% | 3 5.36% 75.00% | 9 16.07% 91.07% | 5 8.93% 100.00% 148911680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.O.PrbInvData::total 56 149011680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.O.PrbShrData | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% 149111680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.O.PrbShrData::total 3 149211680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.M.Load | 0 0.00% 0.00% | 1 14.29% 14.29% | 2 28.57% 42.86% | 0 0.00% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00% 149311680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.M.Load::total 7 149411680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.M.Store | 9 14.06% 14.06% | 11 17.19% 31.25% | 9 14.06% 45.31% | 7 10.94% 56.25% | 9 14.06% 70.31% | 8 12.50% 82.81% | 4 6.25% 89.06% | 7 10.94% 100.00% 149511680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.M.Store::total 64 149611680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.M.PrbInvData | 69 12.02% 12.02% | 73 12.72% 24.74% | 68 11.85% 36.59% | 62 10.80% 47.39% | 79 13.76% 61.15% | 75 13.07% 74.22% | 82 14.29% 88.50% | 66 11.50% 100.00% 149711680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.M.PrbInvData::total 574 149811680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.M.PrbShrData | 14 16.47% 16.47% | 10 11.76% 28.24% | 9 10.59% 38.82% | 8 9.41% 48.24% | 14 16.47% 64.71% | 6 7.06% 71.76% | 14 16.47% 88.24% | 10 11.76% 100.00% 149911680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.M.PrbShrData::total 85 150011680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.I_M.TCC_AckM | 93 13.06% 13.06% | 89 12.50% 25.56% | 86 12.08% 37.64% | 76 10.67% 48.31% | 92 12.92% 61.24% | 89 12.50% 73.74% | 104 14.61% 88.34% | 83 11.66% 100.00% 150111680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.I_M.TCC_AckM::total 712 150211680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.I_ES.TCC_AckS | 9 14.52% 14.52% | 8 12.90% 27.42% | 8 12.90% 40.32% | 12 19.35% 59.68% | 5 8.06% 67.74% | 3 4.84% 72.58% | 8 12.90% 85.48% | 9 14.52% 100.00% 150311680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.I_ES.TCC_AckS::total 62 150411680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.I_ES.TCC_AckE | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% 150511680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.I_ES.TCC_AckE::total 3 150611680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.S_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% 150711680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.S_M.TCC_AckM::total 2 150811680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.O_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 12.50% 12.50% | 0 0.00% 12.50% | 5 62.50% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00% 150911680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.O_M.TCC_AckM::total 8 151011680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.O_M.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 151111680SCurtis.Dunham@arm.comsystem.ruby.TCP_Controller.O_M.PrbShrData::total 2 151211308Santhony.gutierrez@amd.com 151311308Santhony.gutierrez@amd.com---------- End Simulation Statistics ---------- 1514