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/gem5/tests/test-progs/pthread/src/
H A Dtest_pthread_cond.cpp12751:05138dd753f8 Tue Feb 13 09:15:00 EST 2018 Tuan Ta <qtt2@cornell.edu> tests: add some pthread and std::thread unit tests

This patch adds some pthread and C++11 std::thread unit tests.

Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72
Reviewed-on: https://gem5-review.googlesource.com/8221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
H A Dtest_pthread_create_para.cpp12751:05138dd753f8 Tue Feb 13 09:15:00 EST 2018 Tuan Ta <qtt2@cornell.edu> tests: add some pthread and std::thread unit tests

This patch adds some pthread and C++11 std::thread unit tests.

Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72
Reviewed-on: https://gem5-review.googlesource.com/8221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
H A Dtest_pthread_create_seq.cpp12751:05138dd753f8 Tue Feb 13 09:15:00 EST 2018 Tuan Ta <qtt2@cornell.edu> tests: add some pthread and std::thread unit tests

This patch adds some pthread and C++11 std::thread unit tests.

Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72
Reviewed-on: https://gem5-review.googlesource.com/8221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
H A Dtest_pthread_mutex.cpp12751:05138dd753f8 Tue Feb 13 09:15:00 EST 2018 Tuan Ta <qtt2@cornell.edu> tests: add some pthread and std::thread unit tests

This patch adds some pthread and C++11 std::thread unit tests.

Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72
Reviewed-on: https://gem5-review.googlesource.com/8221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
H A Dtest_std_condition_variable.cpp12751:05138dd753f8 Tue Feb 13 09:15:00 EST 2018 Tuan Ta <qtt2@cornell.edu> tests: add some pthread and std::thread unit tests

This patch adds some pthread and C++11 std::thread unit tests.

Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72
Reviewed-on: https://gem5-review.googlesource.com/8221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
H A Dtest_std_mutex.cpp12751:05138dd753f8 Tue Feb 13 09:15:00 EST 2018 Tuan Ta <qtt2@cornell.edu> tests: add some pthread and std::thread unit tests

This patch adds some pthread and C++11 std::thread unit tests.

Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72
Reviewed-on: https://gem5-review.googlesource.com/8221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
H A Dtest_std_thread.cpp12751:05138dd753f8 Tue Feb 13 09:15:00 EST 2018 Tuan Ta <qtt2@cornell.edu> tests: add some pthread and std::thread unit tests

This patch adds some pthread and C++11 std::thread unit tests.

Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72
Reviewed-on: https://gem5-review.googlesource.com/8221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
/gem5/src/mem/cache/prefetch/
H A Dsbooe.cc13735:52ab3bab4f28 Thu Dec 13 17:33:00 EST 2018 Ivan Pizarro <ivan.pizarro@metempsy.com> mem-cache: Sandbox Based Optimal Offset Implementation

Brown, N. T., & Sendag, R. Sandbox Based Optimal Offset Estimation.

Change-Id: Ieb693b6b2c3d8bdfb6948389ca10e92c85454862
Reviewed-on: https://gem5-review.googlesource.com/c/15095
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dsbooe.hh13735:52ab3bab4f28 Thu Dec 13 17:33:00 EST 2018 Ivan Pizarro <ivan.pizarro@metempsy.com> mem-cache: Sandbox Based Optimal Offset Implementation

Brown, N. T., & Sendag, R. Sandbox Based Optimal Offset Estimation.

Change-Id: Ieb693b6b2c3d8bdfb6948389ca10e92c85454862
Reviewed-on: https://gem5-review.googlesource.com/c/15095
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/mem/ruby/slicc_interface/
H A DRubySlicc_includes.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/arch/x86/isa/insts/
H A Dromutil.py5948:871fccb3fb7a Wed Feb 25 13:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement IST stack switching.
5913:f2bfe08dc873 Wed Feb 25 13:18:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Use atCPL0 for accesses that are part of CPU machinery.
5911:8d6e40f38063 Wed Feb 25 13:18:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Move where CS is set so CPL checks work out.
5903:3d7f94358641 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make exceptions handle stack switching.
5680:39ae093fb4eb Mon Oct 13 01:42:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement entering an interrupt in microcode.
/gem5/src/arch/x86/isa/insts/system/
H A Dsegmentation.py5937:177534612ec0 Wed Feb 25 13:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the lldt instruction.
5930:ec124ac0984b Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rename oszForPseudoDesc maxOsz to reflect its more general use.
5927:5e3367b103da Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Do a merge for the zero extension microop.
5902:7a323daa3df2 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the LTR instruction.
5683:e1a1d8bba254 Mon Oct 13 02:00:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement the swapgs instruction.
H A Dcontrol_registers.py5933:8b9bc09b149c Wed Feb 25 13:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement CLTS.
/gem5/src/arch/sparc/solaris/
H A Dsolaris.cc11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps

For O3, which has a stat that counts reg reads, there is an additional
reg read per mmap() call since there's an arg we no longer ignore.
Otherwise, stats should not be affected.
11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct

The structure definition only had the open system call flag set in mind when
it was named, so we rename it here with the intention of using it to define
additional tables to translate flags for other system calls in the future.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/configs/boot/
H A Dnfs-client-dbench.rcS1787:0dcbb68fbea8 Mon Jun 13 11:54:00 EDT 2005 Nathan Binkert <binkertn@umich.edu> Add NFS-dbench, and iscsi dbench benchmarks
/gem5/src/arch/mips/bare_iron/
H A Dsystem.hh5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/arch/power/
H A DPowerISA.py9384:877293183bdf Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@arm.com> arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
/gem5/src/arch/sparc/
H A DSparcISA.py9384:877293183bdf Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@arm.com> arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
/gem5/src/arch/x86/
H A DX86ISA.py9384:877293183bdf Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@arm.com> arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
/gem5/src/arch/x86/insts/
H A Dbadmicroop.hh7966:0dff1ff293d0 Sun Feb 13 20:42:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: On a bad microopc, return a microop that returns a fault that panics.

This way a bad micropc will have to get all the way to commit before killing
the simulation. This accounts for misspeculated branches.
/gem5/src/arch/x86/isa/formats/
H A Dmulti.isa4535:51bf0993137e Fri Jun 08 13:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix up a potentially misleading comment.
4371:c5003760793e Tue Apr 10 13:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Reworked x86 a bit
4323:13ca4002d2ac Tue Apr 03 11:01:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> A batch of changes and fixes. Macroops are now generated automatically, multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.
4310:8f9d834f19bc Thu Mar 29 13:57:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Made the MultiOp format do a little more. It now sets up single microop instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support.
/gem5/util/emacs/
H A Dm5-c-style.el81:6e7e20c22966 Mon Oct 13 11:04:00 EDT 2003 Steve Reinhardt <stever@eecs.umich.edu> Add m5 emacs style file.
/gem5/util/statetrace/arch/sparc/
H A Dtracechild.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/util/statetrace/arch/amd64/
H A Dtracechild.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/util/statetrace/arch/arm/
H A Dtracechild.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes

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