Searched hist:12586 (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/x86/isa/insts/system/ | ||
| H A D | msrs.py | 12586:ab24f7edc1e3 Mon Mar 12 20:41:00 EDT 2018 Gabe Black <gabeblack@google.com> x86: Implement the RDTSCP instruction. This is very similar to RDTSC, except that it requires all younger instructions to retire before it completes, and it writes the TSC_AUX MSR into ECX. I've added an mfence as an iniitial microop to ensure that memory accesses complete before RDTSCP runs, and added an rdval microop at the end to read the TSC_AUX value into ECX. Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9 Reviewed-on: https://gem5-review.googlesource.com/9043 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/arch/x86/isa/decoder/ | ||
| H A D | two_byte_opcodes.isa | 12586:ab24f7edc1e3 Mon Mar 12 20:41:00 EDT 2018 Gabe Black <gabeblack@google.com> x86: Implement the RDTSCP instruction. This is very similar to RDTSC, except that it requires all younger instructions to retire before it completes, and it writes the TSC_AUX MSR into ECX. I've added an mfence as an iniitial microop to ensure that memory accesses complete before RDTSCP runs, and added an rdval microop at the end to read the TSC_AUX value into ECX. Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9 Reviewed-on: https://gem5-review.googlesource.com/9043 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
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