Searched hist:12217 (Results 1 - 4 of 4) sorted by relevance
| /gem5/src/systemc/core/ | ||
| H A D | kernel.cc | 13067:3d6ef32002ef Thu Aug 16 23:59:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Rework the init phase for the new way delta notes are handled. The initialization phase had been done in a somewhat adhoc way, partially because delta notifications were being handled as top level gem5 events which were ordered based on their priorities. This change makes the initialization phase happen more explicitly, and more in the order in the spec. Change-Id: I91d56b63fefcb81c845c52c97826a976a7559fad Reviewed-on: https://gem5-review.googlesource.com/12217 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| H A D | scheduler.hh | 13067:3d6ef32002ef Thu Aug 16 23:59:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Rework the init phase for the new way delta notes are handled. The initialization phase had been done in a somewhat adhoc way, partially because delta notifications were being handled as top level gem5 events which were ordered based on their priorities. This change makes the initialization phase happen more explicitly, and more in the order in the spec. Change-Id: I91d56b63fefcb81c845c52c97826a976a7559fad Reviewed-on: https://gem5-review.googlesource.com/12217 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| H A D | scheduler.cc | 13067:3d6ef32002ef Thu Aug 16 23:59:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Rework the init phase for the new way delta notes are handled. The initialization phase had been done in a somewhat adhoc way, partially because delta notifications were being handled as top level gem5 events which were ordered based on their priorities. This change makes the initialization phase happen more explicitly, and more in the order in the spec. Change-Id: I91d56b63fefcb81c845c52c97826a976a7559fad Reviewed-on: https://gem5-review.googlesource.com/12217 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/cpu/o3/ | ||
| H A D | lsq_unit_impl.hh | 12217:0a16f4c03c02 Thu Jul 27 18:36:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> cpu-o3: Check predication before the SQ size for a debug print The size of the store entry in the LSQ is used to indicate a fault in the execution of the store. At the same time, a store that is predicated false will also have 0 size in the corresponding store queue entry. This changeset ensures that we check if the store was predicated false before checking the size field. This way we avoid printing stores as faulting when they are only predicated false. Change-Id: Ie07982197bd73d7b44d26a3257d54ecb103a952a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4821 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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