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H A D | two_byte_opcodes.isa | 12205:f29b67179a96 Tue Sep 26 12:36:00 EDT 2017 Bjoern A. Zeeb <baz21@cam.ac.uk> arch-x86: fix CondInst decoding for MOV to Control Registers MOV Rd,Cd is MR encoded but the control register is operand 2 not operand 1 hence this needs to be MODRM_REG not MODRM_RM. While MOV Cd,Rd is RM encoded registers are also swapped, so it also needs to be MODRM_REG as well (as it already correctly is). This fixes incorrect UD2 reportings leading to invalid traps reported in O3 on X86 FS introduced with 4e939a7 . Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8 Reviewed-on: https://gem5-review.googlesource.com/4861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
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