Searched hist:12 (Results 826 - 850 of 2449) sorted by relevance
/gem5/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/ | ||
H A D | simerr | 11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches |
/gem5/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/ | ||
H A D | simerr | 11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches |
/gem5/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/ | ||
H A D | config.ini | 11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches |
H A D | config.json | 11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches |
H A D | simout | 11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches |
H A D | simerr | 11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches |
/gem5/src/arch/mips/ | ||
H A D | interrupts.hh | 11566:b11410957c9e Thu Jul 21 12:19:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> isa: Modify get/check interrupt routines Make it so that getInterrupt *always* returns an interrupt if checkInterrupts() returns true. This fixes/simplifies handling of interrupts on the SMT FS CPUs (currently minor). 11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions. 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts. 5646:0a488a147fb8 Sun Oct 12 11:24:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the get_vec function. |
/gem5/src/systemc/ext/utils/ | ||
H A D | _utils.hh | 12852:300397457d0b Fri May 18 05:12:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Stub out all the standard utilility classes and functions. Change-Id: I9e9724edb6281e0b0a6bae5546b0ede77d295c12 Reviewed-on: https://gem5-review.googlesource.com/10841 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
H A D | endian.hh | 12852:300397457d0b Fri May 18 05:12:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Stub out all the standard utilility classes and functions. Change-Id: I9e9724edb6281e0b0a6bae5546b0ede77d295c12 Reviewed-on: https://gem5-review.googlesource.com/10841 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/systemc/utils/ | ||
H A D | sc_vector.cc | 12852:300397457d0b Fri May 18 05:12:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Stub out all the standard utilility classes and functions. Change-Id: I9e9724edb6281e0b0a6bae5546b0ede77d295c12 Reviewed-on: https://gem5-review.googlesource.com/10841 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | uncond.isa | 12788:fe6d6ae79d7c Thu Jun 07 12:17:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: BadMode checking if corresponding EL is implemented The old utility function called badMode was only checking if the mode passed as an argument was a recognized mode. It was not checking if the corresponding mode/EL was implemented. That function has been renamed to unknownMode and a new badMode has been introduced. This is used by the cpsrWriteByInstruction function. In this way any try to change the execution mode won't succeed if the mode hasn't been implemented. Change-Id: Ibfe385c5465b904acc0d2eb9647710891d72c9df Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11196 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> 7605:94b2f78894ca Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: Implement DSB, DMB, ISB 7603:66d853e566d2 Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: Implement CLREX 7602:cd1930acae4e Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: BX instruction can be contitional if last instruction in a IT block Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond. |
/gem5/src/dev/arm/ | ||
H A D | amba_fake.cc | 13230:2988dc5d1d6f Fri Oct 12 07:58:00 EDT 2018 Gabe Black <gabeblack@google.com> arm: Use little endian packet accessors. We know data is little endian, so we can use those accessors explicitly. Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45 Reviewed-on: https://gem5-review.googlesource.com/c/13457 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> 12772:362544959c40 Mon Jun 04 12:50:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> dev-arm: Fix the address range for some I/O devices Previously, many devices were incorrecty configured to respond to an address range of size 0xfff. This changes fixes this and sets it to 0x1000. Change-Id: I4b027a27adf60ceae4859e287d7f34443b398752 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11116 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> 7587:177151a54462 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Change how the AMBA device ID checking is done to make it more generic 7584:28ddf6d9e982 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Add I/O devices for booting linux |
H A D | gic_v2m.cc | 13230:2988dc5d1d6f Fri Oct 12 07:58:00 EDT 2018 Gabe Black <gabeblack@google.com> arm: Use little endian packet accessors. We know data is little endian, so we can use those accessors explicitly. Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45 Reviewed-on: https://gem5-review.googlesource.com/c/13457 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | timer_a9global.cc | 13230:2988dc5d1d6f Fri Oct 12 07:58:00 EDT 2018 Gabe Black <gabeblack@google.com> arm: Use little endian packet accessors. We know data is little endian, so we can use those accessors explicitly. Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45 Reviewed-on: https://gem5-review.googlesource.com/c/13457 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/dev/serial/ | ||
H A D | SConscript | 12689:f554325372e9 Mon Feb 26 12:27:00 EST 2018 Andreas Sandberg <andreas.sandberg@arm.com> dev: Add support for a simple debug UART Add a simple memory-mapped device that forwards writes to a serial devices and treats reads as reads from the device. Unlike real UART models, this one doesn't support interrupts. This is useful to implement various debug devices that exist in many systems. Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10025 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
/gem5/src/mem/cache/replacement_policies/ | ||
H A D | tree_plru_rp.cc | 13236:8ea2f58940b0 Fri Oct 12 16:36:00 EDT 2018 Daniel <odanrc@yahoo.com.br> mem-cache: Add missing includes in TreePLRU Add missing includes to TreePLRU files. Change-Id: Ia1e7b2aa91eec8a30b6dccf513cca37a3058b350 Reviewed-on: https://gem5-review.googlesource.com/c/13477 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | tree_plru_rp.hh | 13236:8ea2f58940b0 Fri Oct 12 16:36:00 EDT 2018 Daniel <odanrc@yahoo.com.br> mem-cache: Add missing includes in TreePLRU Add missing includes to TreePLRU files. Change-Id: Ia1e7b2aa91eec8a30b6dccf513cca37a3058b350 Reviewed-on: https://gem5-review.googlesource.com/c/13477 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/ext/testlib/ | ||
H A D | handlers.py | 12882:dd87d7f2f3e5 Thu Aug 03 12:28:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests,ext: Add a new testing library proposal The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5. Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
H A D | result.py | 12882:dd87d7f2f3e5 Thu Aug 03 12:28:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests,ext: Add a new testing library proposal The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5. Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
H A D | test.py | 12882:dd87d7f2f3e5 Thu Aug 03 12:28:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests,ext: Add a new testing library proposal The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5. Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/mem/slicc/ast/ | ||
H A D | PeekStatementAST.py | 13675:afeab32b3655 Thu Jan 24 19:12:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> python: Replace dict.has_key with 'key in dict' Python 3 has removed dict.has_key in favour of 'key in dict'. Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15987 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> 11111:6da33e720481 Wed Sep 16 12:59:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffer, timer table: significant changes This patch changes MessageBuffer and TimerTable, two structures used for buffering messages by components in ruby. These structures would no longer maintain pointers to clock objects. Functions in these structures have been changed to take as input current time in Tick. Similarly, these structures will not operate on Cycle valued latencies for different operations. The corresponding functions would need to be provided with these latencies by components invoking the relevant functions. These latencies should also be in Ticks. I felt the need for these changes while trying to speed up ruby. The ultimate aim is to eliminate Consumer class and replace it with an EventManager object in the MessageBuffer and TimerTable classes. This object would be used for scheduling events. The event itself would contain information on the object and function to be invoked. In hindsight, it seems I should have done this while I was moving away from use of a single global clock in the memory system. That change led to introduction of clock objects that replaced the global clock object. It never crossed my mind that having clock object pointers is not a good design. And now I really don't like the fact that we have separate consumer, receiver and sender pointers in message buffers. 7007:79413d1ec307 Fri Mar 12 21:42:00 EST 2010 Nathan Binkert <nate@binkert.org> slicc: Change the code generation so that the generated code is easier to read 6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc |
/gem5/tests/gem5/ | ||
H A D | verifier.py | 12882:dd87d7f2f3e5 Thu Aug 03 12:28:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests,ext: Add a new testing library proposal The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5. Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
/gem5/tests/legacy-configs/ | ||
H A D | run.py | 12882:dd87d7f2f3e5 Thu Aug 03 12:28:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests,ext: Add a new testing library proposal The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5. Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/doc/ | ||
H A D | memory_system.doxygen | 9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen |
/gem5/src/mem/cache/prefetch/ | ||
H A D | multi.cc | 13991:102d94094d6b Tue Apr 12 10:10:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> mem-cache: Add multi-prefetcher adaptor This patch adds a meta-prefetcher that enables gem5's cache models to connect to multiple prefetchers. Sub-prefetchers still use the probes-based interface and training can be controlled independently. However, when the cache requests a prefetch packet, the adaptor traverses the priority list of prefetchers and uses the first prefetcher that is able to generate a prefetch. Kudos to Mitch Hayenga for the original version of this patch. Change-Id: I25569a834997e5404c7183ec995d212912c5dcdf Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18868 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
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