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/gem5/src/arch/power/insts/
H A Dinteger.cc6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
H A Dmisc.cc6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/arch/power/isa/formats/
H A Dcondition.isa6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
H A Dformats.isa6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/arch/power/isa/
H A Dmain.isa6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/arch/sparc/
H A Dmicrocode_rom.hh5664:3b3756efad89 Sun Oct 12 18:59:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
/gem5/src/cpu/
H A Ddummy_checker.hh9340:40f8c6a8f38d Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> cpu: Add header files for checker CPUs

In order to create reliable SWIG wrappers, we need to include the
declaration of the wrapped class in the SWIG file. Previously, we
didn't expose the declaration of checker CPUs. This patch adds header
files for such CPUs and include them in the SWIG wrapper.
/gem5/util/
H A Ddiff_config.pl9257:04dfa1898882 Tue Sep 25 12:49:00 EDT 2012 Sascha Bischoff <sascha.bischoff@arm.com> Util: Added script to semantically diff two config.ini files

This script (util/diff_config.pl) takes two config.ini files and compares them.
It highlights value changes, as well as displaying which parts are unique to
a specific config.ini file. This is useful when trying to replicate an earlier
experiment and when trying to make small changes to an existing configuration.
/gem5/src/sim/
H A Dbacktrace.hh11235:4162427127e9 Thu Dec 03 19:12:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Add support for generating back traces on errors

Add functionality to generate a back trace if gem5 crashes (SIGABRT or
SIGSEGV). The current implementation uses glibc's stack traversal
support if available and stubs out the call to print_backtrace()
otherwise.
H A Dbacktrace_none.cc11235:4162427127e9 Thu Dec 03 19:12:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Add support for generating back traces on errors

Add functionality to generate a back trace if gem5 crashes (SIGABRT or
SIGSEGV). The current implementation uses glibc's stack traversal
support if available and stubs out the call to print_backtrace()
otherwise.
H A Dlinear_solver.cc11420:b48c0ba4f524 Tue May 12 05:26:00 EDT 2015 David Guillen Fandos <david.guillen@arm.com> sim: Adding thermal model support

This patch adds basic thermal support to gem5. It models energy dissipation
through a circuital equivalent, which allows us to use RC networks.
This lays down the basic infrastructure to do so, but it does not "work" due
to the lack of power models. For now some hardcoded number is used as a PoC.
The solver is embedded in the patch.
H A Dlinear_solver.hh11420:b48c0ba4f524 Tue May 12 05:26:00 EDT 2015 David Guillen Fandos <david.guillen@arm.com> sim: Adding thermal model support

This patch adds basic thermal support to gem5. It models energy dissipation
through a circuital equivalent, which allows us to use RC networks.
This lays down the basic infrastructure to do so, but it does not "work" due
to the lack of power models. For now some hardcoded number is used as a PoC.
The solver is embedded in the patch.
/gem5/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/src/systemc/ext/utils/
H A Dfunctions.hh12852:300397457d0b Fri May 18 05:12:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Stub out all the standard utilility classes and functions.

Change-Id: I9e9724edb6281e0b0a6bae5546b0ede77d295c12
Reviewed-on: https://gem5-review.googlesource.com/10841
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/tests/systemc/kernel/sc_time/test16/
H A Dexpected_returncode13247:4aafce81e7dd Sat Sep 22 09:12:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add an error check to sc_time.

Change-Id: Ie525a1624a6496a51277fb984cbfeec21eb79749
Reviewed-on: https://gem5-review.googlesource.com/c/12966
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/utils/
H A Dfunctions.cc12852:300397457d0b Fri May 18 05:12:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Stub out all the standard utilility classes and functions.

Change-Id: I9e9724edb6281e0b0a6bae5546b0ede77d295c12
Reviewed-on: https://gem5-review.googlesource.com/10841
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/tests/gem5/hello_se/ref/
H A Dsimerr12885:27839b63374a Thu Aug 03 12:21:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests: Add a simple example test

Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/4422
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
H A Dsimout12885:27839b63374a Thu Aug 03 12:21:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests: Add a simple example test

Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/4422
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
/gem5/tests/test-progs/m5-exit/
H A D.gitignore12886:cba9b724a357 Thu Aug 03 12:22:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests: Add test for the m5-exit instruction.

Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/4423
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
/gem5/tests/test-progs/m5-exit/src/
H A DMakefile.x8612886:cba9b724a357 Thu Aug 03 12:22:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests: Add test for the m5-exit instruction.

Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/4423
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
H A Dm5-exit.c12886:cba9b724a357 Thu Aug 03 12:22:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests: Add test for the m5-exit instruction.

Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/4423
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
/gem5/src/systemc/tests/tlm/endian_conv/
H A DDEPS13527:94ec8e62580e Wed Dec 12 03:17:00 EST 2018 Gabe Black <gabeblack@google.com> systemc: Make input.txt a dependency for the tlm/endian_conv test.

This input file is consumed by the test and needs to be in the build
directory.

Change-Id: I3420dec9e41a1981c7d4e6df47f03273e378ab66
Reviewed-on: https://gem5-review.googlesource.com/c/15064
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
/gem5/util/ccdrv/
H A Ddevtime.c1068:6330fe678283 Wed Aug 18 23:12:00 EDT 2004 Ali Saidi <saidi@eecs.umich.edu> added nate's memtest code to devtime

util/ccdrv/devtime.c:
incorperated nate's changes for memory testing.
1051:d71e55bdc654 Mon Jul 12 22:47:00 EDT 2004 Ali Saidi <saidi@eecs.umich.edu> modified ccdrv to print out raw data.

util/ccdrv/devtime.c:
modified to print out raw data.
996:439a9c897004 Mon Jul 12 23:01:00 EDT 2004 Nathan Binkert <binkertn@umich.edu> put the formatting fixes back into devtime

util/ccdrv/devtime.c:
put the formatting fixes back. no tabs.
994:42291e750752 Mon Jul 12 22:51:00 EDT 2004 Ali Saidi <saidi@eecs.umich.edu> modified devtime to print out raw data
993:bc33dc3beeea Mon Jul 12 22:33:00 EDT 2004 Nathan Binkert <binkertn@umich.edu> formatting
/gem5/src/arch/x86/isa/insts/general_purpose/string/
H A Dscan_string.py5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
5420:dc0041a51920 Thu Jun 12 00:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make string instructions work when rcx=0.

Completed in 43 milliseconds

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