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/gem5/src/cpu/pred/
H A Dmultiperspective_perceptron_tage_64KB.hh14081:f99ed78e5263 Wed Jun 12 09:42:00 EDT 2019 Javier Bueno Hedo <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
H A Dmultiperspective_perceptron_tage_8KB.cc14081:f99ed78e5263 Wed Jun 12 09:42:00 EDT 2019 Javier Bueno Hedo <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
H A Dmultiperspective_perceptron_tage_8KB.hh14081:f99ed78e5263 Wed Jun 12 09:42:00 EDT 2019 Javier Bueno Hedo <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/
H A Dmove.py12584:2af98e1fb894 Mon Mar 12 20:06:00 EDT 2018 Gabe Black <gabeblack@google.com> x86: Replace the .serializing directive with .serialize_(before|after).

This makes it explicit which type of serialization you want, and also
makes it possible to make a macroop serialize before. The old
serializing directive was renamed .serialize_after in the microcode
assembler, and throughout the microcode implementation, and its
behavior is unchanged. More specifically, it still marks the last
microop within the macroop as IsSerializing and IsSerializeAfter.

The new .serialize_before directive does something similar and marks
the first microop as IsSerializing and IsSerializeBefore.

Change-Id: Ia53466c734c651c65400809de7ef903c4a6c3e7e
Reviewed-on: https://gem5-review.googlesource.com/9041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
7622:b49144029ec8 Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Mark serializing macroops and regular instructions as such.
5974:9ed073dd5214 Fri Feb 27 12:26:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set address size to 64 bits when generating addresses internally.
5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
5433:1b0b8e9ba6a9 Thu Jun 12 00:52:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Change how segment loading is performed.
5413:809f33a926c4 Thu Jun 12 00:45:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Fix a byte register indexing issue in the sign extending move from memory microcode.
5241:a6602acdd046 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the wrcr microop which writes a control register, and some control register work.
5239:0920dfb94514 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.
5151:dec27c6c2b3b Fri Oct 12 23:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Added some new versions of MOV and a new argument type tag.
/gem5/src/base/filters/
H A Dperfect_bloom_filter.cc14268:3012cd98980d Sun May 12 17:17:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> base: Add a perfect bloom filter

Add a bloom filter that keeps track of all observed entries, and
thus has no false negatives nor false positives.

Change-Id: Iba784e617a99c77554c688470d9b9e12c260f23b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18879
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dperfect_bloom_filter.hh14268:3012cd98980d Sun May 12 17:17:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> base: Add a perfect bloom filter

Add a bloom filter that keeps track of all observed entries, and
thus has no false negatives nor false positives.

Change-Id: Iba784e617a99c77554c688470d9b9e12c260f23b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18879
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/dev/arm/
H A Ddisplay.cc14283:b02cde4661e1 Mon Aug 12 14:56:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Add HDLcd DTB autogeneration

A Display has been defined. Its sole purpose is to generate the device
tree node to be referenced by the HDLcd device. The encoder parameters
are based on the existing node defined in:

system/arm/dt/armv8.dts

Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Ddisplay.hh14283:b02cde4661e1 Mon Aug 12 14:56:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Add HDLcd DTB autogeneration

A Display has been defined. Its sole purpose is to generate the device
tree node to be referenced by the HDLcd device. The encoder parameters
are based on the existing node defined in:

system/arm/dt/armv8.dts

Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A DDisplay.py14283:b02cde4661e1 Mon Aug 12 14:56:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Add HDLcd DTB autogeneration

A Display has been defined. Its sole purpose is to generate the device
tree node to be referenced by the HDLcd device. The encoder parameters
are based on the existing node defined in:

system/arm/dt/armv8.dts

Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/arch/power/
H A Dfaults.hh6972:b6482c4c89e3 Fri Feb 12 14:53:00 EST 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.
6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/arch/x86/isa/insts/general_purpose/flags/
H A Dpush_and_pop.py5432:e1e42f18d376 Thu Jun 12 00:51:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make pushes and pops use the stack size instead of the data size.
5426:0bdcc60ccc45 Thu Jun 12 00:49:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add microops and supporting code to manipulate the whole rflags register.
/gem5/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/
H A Dshift.py5977:4fff54ab52ae Fri Feb 27 12:26:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement shrd.
5961:969fb3187eba Fri Feb 27 12:23:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Compute shift instruction flags correctly.
/gem5/src/arch/x86/isa/insts/general_purpose/string/
H A Dmove_string.py5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
5420:dc0041a51920 Thu Jun 12 00:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make string instructions work when rcx=0.
H A Dstore_string.py5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
5420:dc0041a51920 Thu Jun 12 00:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make string instructions work when rcx=0.
/gem5/src/mem/probes/
H A Dbase.hh11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
11001:80f018934c3a Wed Aug 05 05:12:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> mem: Fixup incorrect include guards
/gem5/src/mem/slicc/ast/
H A DOperatorExprAST.py11016:bc759340631f Tue Aug 11 12:39:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: allow mathematical operations on Ticks
9692:67d9da312ef0 Tue May 21 12:31:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu>, Malek Musleh <malek.musleh@gmail.com> ruby: add stats to .sm files, remove cache profiler
This patch changes the way cache statistics are collected in ruby.

As of now, there is separate entity called CacheProfiler which holds
statistical variables for caches. The CacheMemory class defines different
functions for accessing the CacheProfiler. These functions are then invoked
in the .sm files. I find this approach opaque and prone to error. Secondly,
we probably should not be paying the cost of a function call for recording
statistics.

Instead, this patch allows for accessing statistical variables in the
.sm files. The collection would become transparent. Secondly, it would happen
in place, so no function calls. The patch also removes the CacheProfiler class.
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/
H A Dsimout11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
/gem5/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/
H A Dconfig.ini11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
H A Dsimout11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
/gem5/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/
H A Dconfig.ini11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
H A Dsimout11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
/gem5/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/
H A Dconfig.ini11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
H A Dsimout11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
/gem5/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/
H A Dconfig.ini11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP

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