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/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/se/50.vortex/ref/arm/linux/minor-timing/
H A Dstats.txt11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
/gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/
H A Dsimout11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
9013:afa278317136 Tue May 22 12:38:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> X86 Regression: update stats due to cc register split
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/
H A Dsimerr11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/
H A Dsimerr11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/tests/test-progs/insttest/src/riscv/
H A Drv64a.cpp11730:08ab68477ea0 Wed Nov 30 17:12:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 8/5] Added some regression tests to RISC-V

This patch is the eighth patch in a series adding RISC-V to gem5, and
third of the bonus patches to the original series of five. It adds some
regression tests to RISC-V.

Regression tests included:
- se/00.hello
- se/02.insttest (split into several binaries which are not included due
to large size)

The tests added to 00.insttest will need to be build manually; to
facilitate this, a Makefile is included. The required toolchain and
compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools
GitHub repository at https://github.com/riscv/riscv-tools.

Note that because EBREAK only makes sense when gdb is running or while in
FS mode, it is not included in the linux-rv64i insttest. ERET is not
included because it does not make sense in SE mode and, in fact, causes
a panic by design.

Note also that not every system call is tested in linux-rv64i; of the ones
defined in linux/process.hh, some have been given numbers but not
definitions for the toolchain, or are merely stubs that always return 0. Of
the ones that do work properly, only a subset are tested due to similar
functionality.

Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
H A Dinsttest.h11730:08ab68477ea0 Wed Nov 30 17:12:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 8/5] Added some regression tests to RISC-V

This patch is the eighth patch in a series adding RISC-V to gem5, and
third of the bonus patches to the original series of five. It adds some
regression tests to RISC-V.

Regression tests included:
- se/00.hello
- se/02.insttest (split into several binaries which are not included due
to large size)

The tests added to 00.insttest will need to be build manually; to
facilitate this, a Makefile is included. The required toolchain and
compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools
GitHub repository at https://github.com/riscv/riscv-tools.

Note that because EBREAK only makes sense when gdb is running or while in
FS mode, it is not included in the linux-rv64i insttest. ERET is not
included because it does not make sense in SE mode and, in fact, causes
a panic by design.

Note also that not every system call is tested in linux-rv64i; of the ones
defined in linux/process.hh, some have been given numbers but not
definitions for the toolchain, or are merely stubs that always return 0. Of
the ones that do work properly, only a subset are tested due to similar
functionality.

Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/sim/power/
H A DThermalDomain.py11420:b48c0ba4f524 Tue May 12 05:26:00 EDT 2015 David Guillen Fandos <david.guillen@arm.com> sim: Adding thermal model support

This patch adds basic thermal support to gem5. It models energy dissipation
through a circuital equivalent, which allows us to use RC networks.
This lays down the basic infrastructure to do so, but it does not "work" due
to the lack of power models. For now some hardcoded number is used as a PoC.
The solver is embedded in the patch.
/gem5/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/
H A Dstats.txt11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
/gem5/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/
H A Dstats.txt11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
/gem5/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/
H A Dstats.txt11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
/gem5/tests/test-progs/hello/bin/riscv/linux/
H A Dhello11730:08ab68477ea0 Wed Nov 30 17:12:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 8/5] Added some regression tests to RISC-V

This patch is the eighth patch in a series adding RISC-V to gem5, and
third of the bonus patches to the original series of five. It adds some
regression tests to RISC-V.

Regression tests included:
- se/00.hello
- se/02.insttest (split into several binaries which are not included due
to large size)

The tests added to 00.insttest will need to be build manually; to
facilitate this, a Makefile is included. The required toolchain and
compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools
GitHub repository at https://github.com/riscv/riscv-tools.

Note that because EBREAK only makes sense when gdb is running or while in
FS mode, it is not included in the linux-rv64i insttest. ERET is not
included because it does not make sense in SE mode and, in fact, causes
a panic by design.

Note also that not every system call is tested in linux-rv64i; of the ones
defined in linux/process.hh, some have been given numbers but not
definitions for the toolchain, or are merely stubs that always return 0. Of
the ones that do work properly, only a subset are tested due to similar
functionality.

Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/mem/probes/
H A Dmem_trace.cc11437:210624864179 Thu Apr 07 12:32:00 EDT 2016 Victor Garcia <victor.garcia@arm.com> mem: Add Program Counter to MemTraceProbe
/gem5/src/sim/
H A DClockedObject.py12265:7db0f21ff605 Fri Jul 01 12:46:00 EDT 2016 David Guillen Fandos <david.guillen@arm.com> pwr: Enable multiple power models per component

This patch allows the user to specify more than one
power model for any given Clocked Object. This is
useful and some times necessary to properly model
components that have multiple power sources (or
subcomponents) but gem5 doesn't model them.

The ideal solution would be to have a DictParam
to replace the VectorParam so each model can have
a name and can be identified in the stats file.

Change-Id: I4080a7054a16b56069c44750a7a9ce4e674cdf9d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5733
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
11527:9007a9729815 Mon Jun 06 12:16:00 EDT 2016 David Guillen Fandos <david.guillen@arm.com> sim: Adding support for power models

This patch adds some basic support for power models in gem5.

The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.

The model allows it to be extended to use other kinds of models.

Change-Id: I76752f9638b6815e229fd74cdcb7721a305cbc4b
11524:3101ce98c55c Mon Jun 06 12:16:00 EDT 2016 David Guillen Fandos <david.guillen@arm.com> pwr: Add power states to ClockedObject

Add 4 power states to the ClockedObject, provides necessary access
functions to check and update the power state. Default power state
is UNDEFINED, it is responsibility of the respective simulation
model to provide the startup state and any other logic for state
change. Add number of transition stat. Add distribution of time
spent in clock gated state. Add power state residency stat. Add
dump call back function to allow stats update of distribution
and residency stats.

Change-Id: Id086090a2ed720c9fcb37812a3c98f0f724907c6
9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
H A Dmathexpr.cc11527:9007a9729815 Mon Jun 06 12:16:00 EDT 2016 David Guillen Fandos <david.guillen@arm.com> sim: Adding support for power models

This patch adds some basic support for power models in gem5.

The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.

The model allows it to be extended to use other kinds of models.

Change-Id: I76752f9638b6815e229fd74cdcb7721a305cbc4b
/gem5/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/
H A Dconfig.ini11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/src/systemc/channel/
H A Dsc_semaphore.cc13298:0a0a0aad1b4a Fri Oct 05 19:12:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add a range check to the intial value of sc_semaphore.

Change-Id: I4e1ef90b14074e5a2794a4386e411397213b2789
Reviewed-on: https://gem5-review.googlesource.com/c/13304
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/core/
H A Dsc_join.cc12943:12c1004709d4 Mon Jun 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add the nonstandard sc_join class and sc_thread_handle type.

Change-Id: I09905bad4797d9c456229afe601006ce16977394
Reviewed-on: https://gem5-review.googlesource.com/11353
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

Completed in 73 milliseconds

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