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/gem5/src/cpu/
H A Ddummy_checker.cc11150:a8a64cca231b Wed Sep 30 12:14:00 EDT 2015 Mitch Hayenga <mitch.hayenga@arm.com> isa,cpu: Add support for FS SMT Interrupts

Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
9340:40f8c6a8f38d Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> cpu: Add header files for checker CPUs

In order to create reliable SWIG wrappers, we need to include the
declaration of the wrapped class in the SWIG file. Previously, we
didn't expose the declaration of checker CPUs. This patch adds header
files for such CPUs and include them in the SWIG wrapper.
/gem5/src/python/m5/internal/
H A D__init__.py9342:6fec8f26e56d Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Move the draining interface into a separate base class

This patch moves the draining interface from SimObject to a separate
class that can be used by any object needing draining. However,
objects not visible to the Python code (i.e., objects not deriving
from SimObject) still depend on their parents informing them when to
drain. This patch also gets rid of the CountedDrainEvent (which isn't
really an event) and replaces it with a DrainManager.
/gem5/src/sim/
H A Dasync.hh9990:12a0efdde000 Fri Nov 29 08:36:00 EST 2013 Andreas Sandberg <andreas@sandberg.pp.se> base: Fix race in PollQueue and remove SIGALRM workaround

There is a race between enabling asynchronous IO for a file descriptor
and IO events happening on that descriptor. A SIGIO won't normally be
delivered if an event is pending when asynchronous IO is
enabled. Instead, the signal will be raised the next time there is an
event on the FD. This changeset simulates a SIGIO by setting the
async_io flag when setting up asynchronous IO for an FD. This causes
the main event loop to poll all file descriptors to check for pending
IO. As a consequence of this, the old SIGALRM hack should no longer be
needed and is therefore removed.
H A Dmathexpr.hh11527:9007a9729815 Mon Jun 06 12:16:00 EDT 2016 David Guillen Fandos <david.guillen@arm.com> sim: Adding support for power models

This patch adds some basic support for power models in gem5.

The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.

The model allows it to be extended to use other kinds of models.

Change-Id: I76752f9638b6815e229fd74cdcb7721a305cbc4b
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/
H A Dsimerr9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
/gem5/configs/boot/
H A Dnetperf-server.rcS1142:f31491939594 Fri Nov 12 15:03:00 EST 2004 Lisa Hsu <hsul@eecs.umich.edu> add surge and spec-surge readfiles. also make the naming system uniform, there were 3 different ways!!! i like ali's.
/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/
H A Dmultiply_and_divide.py5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
/gem5/src/arch/x86/
H A Dvtophys.hh4162:baef0678866b Mon Mar 05 12:59:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Fill out a stub version of the vtophys header file.
/gem5/src/base/vnc/
H A DSConscript9330:4a3269a11230 Fri Nov 02 12:32:00 EDT 2012 Chander Sudanthi <chander.sudanthi@arm.com> base: split out the VncServer into a VncInput and Server classes

This patch adds a VncInput base class which VncServer inherits from.
Another class can implement the same interface and be used instead
of the VncServer, for example a class that replays Vnc traffic.
/gem5/src/mem/ruby/structures/
H A DTimerTable.hh11111:6da33e720481 Wed Sep 16 12:59:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffer, timer table: significant changes

This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby. These structures would no longer
maintain pointers to clock objects. Functions in these structures have been
changed to take as input current time in Tick. Similarly, these structures
will not operate on Cycle valued latencies for different operations. The
corresponding functions would need to be provided with these latencies by
components invoking the relevant functions. These latencies should also be
in Ticks.

I felt the need for these changes while trying to speed up ruby. The ultimate
aim is to eliminate Consumer class and replace it with an EventManager object in
the MessageBuffer and TimerTable classes. This object would be used for
scheduling events. The event itself would contain information on the object and
function to be invoked.

In hindsight, it seems I should have done this while I was moving away from use
of a single global clock in the memory system. That change led to introduction
of clock objects that replaced the global clock object. It never crossed my
mind that having clock object pointers is not a good design. And now I really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.
/gem5/src/mem/slicc/ast/
H A DEnumDeclAST.py6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
H A DTypeFieldEnumAST.py6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/
H A Dsystem.terminal9370:5172ffaf6e30 Wed Dec 12 10:51:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> arm regressions: updates to config.ini, terminal files
/gem5/src/arch/x86/isa/insts/general_purpose/
H A Dsystem_calls.py6344:b7104eda0795 Thu Jul 16 12:27:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix a number of places where the wrong form of a microop was used.
/gem5/src/arch/power/linux/
H A Dlinux.cc6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/
H A Dconfig.ini11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
/gem5/src/mem/probes/
H A Dstack_dist.cc11523:81332eb10367 Mon Jun 06 12:16:00 EDT 2016 David Guillen Fandos <david.guillen@arm.com> stats: Fixing regStats function for some SimObjects

Fixing an issue with regStats not calling the parent class method
for most SimObjects in Gem5. This causes issues if one adds new
stats in the base class (since they are never initialized properly!).

Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/cpu/minor/
H A Dexecute.hh11567:560d7fbbddd1 Thu Jul 21 12:19:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Add SMT support to MinorCPU

This patch adds SMT support to the MinorCPU. Currently
RoundRobin or Random thread scheduling are supported.

Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
H A Ddecode.hh11567:560d7fbbddd1 Thu Jul 21 12:19:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Add SMT support to MinorCPU

This patch adds SMT support to the MinorCPU. Currently
RoundRobin or Random thread scheduling are supported.

Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
H A Dpipe_data.hh11567:560d7fbbddd1 Thu Jul 21 12:19:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Add SMT support to MinorCPU

This patch adds SMT support to the MinorCPU. Currently
RoundRobin or Random thread scheduling are supported.

Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
H A Dpipe_data.cc11567:560d7fbbddd1 Thu Jul 21 12:19:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Add SMT support to MinorCPU

This patch adds SMT support to the MinorCPU. Currently
RoundRobin or Random thread scheduling are supported.

Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
/gem5/util/minorview/
H A Dminor.pic11567:560d7fbbddd1 Thu Jul 21 12:19:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Add SMT support to MinorCPU

This patch adds SMT support to the MinorCPU. Currently
RoundRobin or Random thread scheduling are supported.

Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
/gem5/src/dev/storage/
H A Ddisk_image.hh11442:b31738224fb0 Tue Apr 12 05:28:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> misc: Appease clang...again

Once again, clang is having issues with recently committed code.

Unfortunately HSAIL_X86 is still broken.
/gem5/src/dev/arm/
H A Dgpu_nomali.hh11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/
H A Dconfig.ini11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references

Completed in 69 milliseconds

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