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| /gem5/src/mem/cache/ | ||
| H A D | cache.cc | 11333:c41d552d6f2e Wed Feb 10 04:08:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> mem: Align cache behaviour in atomic when upstream is responding Adopt the same flow as in timing mode, where the caches on the path to memory get to keep the line (if present), and we use the responderHadWritable flag to determine if we need to forward the (invalidating) packet or not. |
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