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/gem5/src/mem/slicc/ast/
H A DOperatorExprAST.py11016:bc759340631f Tue Aug 11 12:39:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: allow mathematical operations on Ticks
/gem5/src/mem/cache/
H A Dmshr.hh12792:9af3470e24e7 Fri Mar 16 20:52:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix promoting of targets that need writable

There are cases where a request which does not need a writable copy
gets an response upgraded reponse and fills in a writable copy. When
this happens, we promote deferred MSHR targets that were deferred
because they needed a writable copy to service them immediately.

Previously, we would uncoditionally promote deferred targets. Since
the deferred targets might contain a cache invalidation operation, we
have to make sure that any targets following the cache invalidation is
not promoted.

Change-Id: I1f7b28f7d35f84329e065c8f63117db21852365a
Reviewed-on: https://gem5-review.googlesource.com/11016
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A Dmshr.cc12792:9af3470e24e7 Fri Mar 16 20:52:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix promoting of targets that need writable

There are cases where a request which does not need a writable copy
gets an response upgraded reponse and fills in a writable copy. When
this happens, we promote deferred MSHR targets that were deferred
because they needed a writable copy to service them immediately.

Previously, we would uncoditionally promote deferred targets. Since
the deferred targets might contain a cache invalidation operation, we
have to make sure that any targets following the cache invalidation is
not promoted.

Change-Id: I1f7b28f7d35f84329e065c8f63117db21852365a
Reviewed-on: https://gem5-review.googlesource.com/11016
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

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