Searched hist:10504 (Results 1 - 7 of 7) sorted by relevance
| /gem5/src/arch/arm/isa/formats/ | ||
| H A D | misc.isa | 12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | aarch64.isa | 12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/ | ||
| H A D | ArmISA.py | 12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | miscregs.cc | 12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | isa.hh | 12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | isa.cc | 12714:6870e0c151b1 Wed May 09 12:52:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/cpu/minor/ | ||
| H A D | lsq.cc | 10504:58d5d471b598 Thu Oct 30 00:18:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Fix barrier push to store buffer when full bug in Minor This patch fixes a bug where a completing load or store which is also a barrier can push a barrier into the store buffer without first checking that there is a free slot. The bug was not fatal but would print a warning that the store buffer was full when inserting. |
Completed in 98 milliseconds