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| /gem5/src/mem/ | ||
| H A D | packet.cc | 10345:b5bef3c8e070 Fri Jun 27 01:29:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> mem: write streaming support via WriteInvalidate promotion Support full-block writes directly rather than requiring RMW: * a cache line is allocated in the cache upon receipt of a WriteInvalidateReq, not the WriteInvalidateResp. * only top-level caches allocate the line; the others just pass the request along and invalidate as necessary. * to close a timing window between the *Req and the *Resp, a new metadata bit tracks whether another cache has read a copy of the new line before the writeback to memory. |
| H A D | packet.hh | 10345:b5bef3c8e070 Fri Jun 27 01:29:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> mem: write streaming support via WriteInvalidate promotion Support full-block writes directly rather than requiring RMW: * a cache line is allocated in the cache upon receipt of a WriteInvalidateReq, not the WriteInvalidateResp. * only top-level caches allocate the line; the others just pass the request along and invalidate as necessary. * to close a timing window between the *Req and the *Resp, a new metadata bit tracks whether another cache has read a copy of the new line before the writeback to memory. |
| /gem5/src/mem/cache/ | ||
| H A D | cache.hh | 10345:b5bef3c8e070 Fri Jun 27 01:29:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> mem: write streaming support via WriteInvalidate promotion Support full-block writes directly rather than requiring RMW: * a cache line is allocated in the cache upon receipt of a WriteInvalidateReq, not the WriteInvalidateResp. * only top-level caches allocate the line; the others just pass the request along and invalidate as necessary. * to close a timing window between the *Req and the *Resp, a new metadata bit tracks whether another cache has read a copy of the new line before the writeback to memory. |
| H A D | base.hh | 10345:b5bef3c8e070 Fri Jun 27 01:29:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> mem: write streaming support via WriteInvalidate promotion Support full-block writes directly rather than requiring RMW: * a cache line is allocated in the cache upon receipt of a WriteInvalidateReq, not the WriteInvalidateResp. * only top-level caches allocate the line; the others just pass the request along and invalidate as necessary. * to close a timing window between the *Req and the *Resp, a new metadata bit tracks whether another cache has read a copy of the new line before the writeback to memory. |
| H A D | base.cc | 10345:b5bef3c8e070 Fri Jun 27 01:29:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> mem: write streaming support via WriteInvalidate promotion Support full-block writes directly rather than requiring RMW: * a cache line is allocated in the cache upon receipt of a WriteInvalidateReq, not the WriteInvalidateResp. * only top-level caches allocate the line; the others just pass the request along and invalidate as necessary. * to close a timing window between the *Req and the *Resp, a new metadata bit tracks whether another cache has read a copy of the new line before the writeback to memory. |
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