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/gem5/src/mem/cache/ | ||
H A D | cache.hh | 10343:a1eea45928e6 Tue May 13 01:20:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> cpu, mem: Make software prefetches non-blocking Previously, they were treated so much like loads that they could stall at the head of the ROB. Now they are always treated like L1 hits. If they actually miss, a new request is created at the L1 and tracked from the MSHRs there if necessary (i.e. if it didn't coalesce with an existing outstanding load). |
/gem5/src/mem/ | ||
H A D | packet.hh | 10343:a1eea45928e6 Tue May 13 01:20:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> cpu, mem: Make software prefetches non-blocking Previously, they were treated so much like loads that they could stall at the head of the ROB. Now they are always treated like L1 hits. If they actually miss, a new request is created at the L1 and tracked from the MSHRs there if necessary (i.e. if it didn't coalesce with an existing outstanding load). |
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