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| /gem5/src/cpu/o3/ | ||
| H A D | O3CPU.py | 10327:5b6279635c49 Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Change writeback modeling for outstanding instructions As highlighed on the mailing list gem5's writeback modeling can impact performance. This patch removes the limitation on maximum outstanding issued instructions, however the number that can writeback in a single cycle is still respected in instToCommit(). |
| H A D | iew.hh | 10327:5b6279635c49 Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Change writeback modeling for outstanding instructions As highlighed on the mailing list gem5's writeback modeling can impact performance. This patch removes the limitation on maximum outstanding issued instructions, however the number that can writeback in a single cycle is still respected in instToCommit(). |
| H A D | lsq_unit.hh | 10327:5b6279635c49 Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Change writeback modeling for outstanding instructions As highlighed on the mailing list gem5's writeback modeling can impact performance. This patch removes the limitation on maximum outstanding issued instructions, however the number that can writeback in a single cycle is still respected in instToCommit(). |
| H A D | inst_queue_impl.hh | 10327:5b6279635c49 Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Change writeback modeling for outstanding instructions As highlighed on the mailing list gem5's writeback modeling can impact performance. This patch removes the limitation on maximum outstanding issued instructions, however the number that can writeback in a single cycle is still respected in instToCommit(). |
| H A D | iew_impl.hh | 10327:5b6279635c49 Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Change writeback modeling for outstanding instructions As highlighed on the mailing list gem5's writeback modeling can impact performance. This patch removes the limitation on maximum outstanding issued instructions, however the number that can writeback in a single cycle is still respected in instToCommit(). |
| H A D | lsq_unit_impl.hh | 10327:5b6279635c49 Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Change writeback modeling for outstanding instructions As highlighed on the mailing list gem5's writeback modeling can impact performance. This patch removes the limitation on maximum outstanding issued instructions, however the number that can writeback in a single cycle is still respected in instToCommit(). |
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