Searched defs:mem_side (Results 1 - 4 of 4) sorted by relevance

/gem5/src/learning_gem5/part2/
H A DSimpleMemobj.py39 mem_side = MasterPort("Memory side port, sends requests") variable in class:SimpleMemobj
H A DSimpleCache.py41 mem_side = MasterPort("Memory side port, sends requests") variable in class:SimpleCache
/gem5/src/mem/
H A DMemChecker.py54 mem_side = MasterPort("Alias for master") variable in class:MemCheckerMonitor
/gem5/src/mem/cache/
H A DCache.py114 mem_side = MasterPort("Downstream port closer to memory") variable in class:BaseCache

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