Searched defs:dcache_port (Results 1 - 3 of 3) sorted by relevance

/gem5/src/cpu/checker/
H A Dcpu.cc128 CheckerCPU::setDcachePort(MasterPort *dcache_port) argument
/gem5/src/cpu/
H A DBaseCPU.py213 dcache_port = MasterPort("Data Port") variable in class:BaseCPU
/gem5/src/cpu/o3/
H A Dlsq_unit_impl.hh251 LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) argument

Completed in 10 milliseconds