Searched defs:cacheLoadPorts (Results 1 - 2 of 2) sorted by relevance

/gem5/src/cpu/o3/
H A DO3CPU.py81 cacheLoadPorts = Param.Unsigned(200, "Cache Ports. " variable in class:DerivO3CPU
H A Dlsq.hh1064 int cacheLoadPorts; member in class:LSQ::LSQRequest

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