Searched defs:OUT_VALUE1 (Results 1 - 25 of 50) sorted by relevance

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/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/
H A Dstimulus.h57 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal<int>& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
H A Ddecrement.h66 decrement( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal<int>& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal<bool>& IN_VALID, sc_signal<bool>& OUT_ACK, sc_signal<int>& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/
H A Dincrement.h64 increment( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal<int>& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal<bool>& IN_VALID, sc_signal<int>& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/
H A Dstimulus.h59 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector2& OUT_VALUE1, sc_signal_bool_vector2& OUT_VALUE2, sc_signal_bool_vector3& OUT_VALUE3, sc_signal_bool_vector3& OUT_VALUE4, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
H A Ddatatypes.h71 datatypes( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector2& IN_VALUE1, const sc_signal_bool_vector2& IN_VALUE2, const sc_signal_bool_vector3& IN_VALUE3, const sc_signal_bool_vector3& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector2& OUT_VALUE1, sc_signal_bool_vector2& OUT_VALUE2, sc_signal_bool_vector3& OUT_VALUE3, sc_signal_bool_vector3& OUT_VALUE4, sc_signal<bool>& OUT_ACK, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/
H A Dstimulus.h59 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector2& OUT_VALUE1, sc_signal_bool_vector4& OUT_VALUE2, sc_signal_bool_vector6& OUT_VALUE3, sc_signal_bool_vector8& OUT_VALUE4, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
H A Dbitwidth.h71 bitwidth( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector2& IN_VALUE1, const sc_signal_bool_vector4& IN_VALUE2, const sc_signal_bool_vector6& IN_VALUE3, const sc_signal_bool_vector8& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector2& OUT_VALUE1, sc_signal_bool_vector4& OUT_VALUE2, sc_signal_bool_vector6& OUT_VALUE3, sc_signal_bool_vector8& OUT_VALUE4, sc_signal<bool>& OUT_ACK, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/
H A Dstimulus.h60 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector4& OUT_VALUE1, sc_signal_bool_vector5& OUT_VALUE2, sc_signal_bool_vector6& OUT_VALUE3, sc_signal_bool_vector7& OUT_VALUE4, sc_signal_bool_vector8& OUT_VALUE5, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/
H A Dstimulus.h60 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<long>& OUT_VALUE3, sc_signal<int>& OUT_VALUE4, sc_signal<short>& OUT_VALUE5, sc_signal<char>& OUT_VALUE6, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/
H A Dstimulus.h61 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<long>& OUT_VALUE3, sc_signal<int>& OUT_VALUE4, sc_signal<short>& OUT_VALUE5, sc_signal<char>& OUT_VALUE6, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/
H A Dstimulus.h62 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<long>& OUT_VALUE3, sc_signal<int>& OUT_VALUE4, sc_signal<short>& OUT_VALUE5, sc_signal<char>& OUT_VALUE6, sc_signal<char>& OUT_VALUE7, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/
H A Dstimulus.h61 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<long>& OUT_VALUE3, sc_signal<int>& OUT_VALUE4, sc_signal<short>& OUT_VALUE5, sc_signal<char>& OUT_VALUE6, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/
H A Dstimulus.h61 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<long>& OUT_VALUE3, sc_signal<int>& OUT_VALUE4, sc_signal<short>& OUT_VALUE5, sc_signal<char>& OUT_VALUE6, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/
H A Dstimulus.h61 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<long>& OUT_VALUE3, sc_signal<int>& OUT_VALUE4, sc_signal<short>& OUT_VALUE5, sc_signal<char>& OUT_VALUE6, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/
H A Dbalancing.h63 balancing( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal<bool>& OUT_VALID1, sc_signal<bool>& OUT_VALID2, sc_signal<bool>& OUT_VALID3 ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/
H A Ddatatypes.h63 datatypes( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal_bool_vector& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal_bool_vector& OUT_VALUE4, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/
H A Dfsm.h63 fsm( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal<bool>& OUT_VALID1, sc_signal<bool>& OUT_VALID2, sc_signal<bool>& OUT_VALID3 ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/
H A Dinlining.h61 inlining( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal_bool_vector& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/
H A Dbalancing.h63 balancing( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal<bool>& OUT_VALID1, sc_signal<bool>& OUT_VALID2, sc_signal<bool>& OUT_VALID3 ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/
H A Ddatatypes.h63 datatypes( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal_bool_vector& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal_bool_vector& OUT_VALUE4, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/
H A Dfsm.h63 fsm( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal<bool>& OUT_VALID1, sc_signal<bool>& OUT_VALID2, sc_signal<bool>& OUT_VALID3 ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/
H A Dinlining.h61 inlining( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal_bool_vector& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/stars/star110069/
H A Dmem0.h67 mem0( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<bool>& OUT_VALID, int *MEMORY ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/
H A Daddition.h70 addition( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal<int>& IN_VALUE1, const sc_signal_bool_vector4& IN_VALUE2, const sc_signal_bool_vector4& IN_VALUE3, const sc_signal_bool_vector8& IN_VALUE4, const sc_signal_bool_vector8& IN_VALUE5, const sc_signal<bool>& IN_VALID, sc_signal<int>& OUT_VALUE1, sc_signal_bool_vector4& OUT_VALUE2, sc_signal_bool_vector4& OUT_VALUE3, sc_signal_bool_vector8& OUT_VALUE4, sc_signal_bool_vector8& OUT_VALUE5, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/
H A Dbitwidth.h72 bitwidth( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector4& IN_VALUE1, const sc_signal_bool_vector4& IN_VALUE2, const sc_signal_bool_vector6& IN_VALUE3, const sc_signal_bool_vector6& IN_VALUE4, const sc_signal_bool_vector8& IN_VALUE5, const sc_signal_bool_vector8& IN_VALUE6, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector4& OUT_VALUE1, sc_signal_bool_vector4& OUT_VALUE2, sc_signal_bool_vector6& OUT_VALUE3, sc_signal_bool_vector6& OUT_VALUE4, sc_signal_bool_vector8& OUT_VALUE5, sc_signal_bool_vector8& OUT_VALUE6, sc_signal<bool>& OUT_VALID ) argument

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