xref: /gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/stimulus.h

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  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
  more contributor license agreements.  See the NOTICE file distributed
  with this work for additional information regarding copyright ownership.
  Accellera licenses this file to you under the Apache License, Version 2.0
  (the "License"); you may not use this file except in compliance with the
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    http://www.apache.org/licenses/LICENSE-2.0

  Unless required by applicable law or agreed to in writing, software
  distributed under the License is distributed on an "AS IS" BASIS,
  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
  implied.  See the License for the specific language governing
  permissions and limitations under the License.

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/*****************************************************************************

  stimulus.h --

  Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30

 *****************************************************************************/

/*****************************************************************************

  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
  changes you are making here.

      Name, Affiliation, Date:
  Description of Modification:

 *****************************************************************************/


#include "common.h"

SC_MODULE( stimulus )
{
    SC_HAS_PROCESS( stimulus );

    sc_in_clk clk;

    sc_signal<bool>&             reset ;
    sc_signal_bool_vector2&      out_value1;     // Output  port
    sc_signal_bool_vector2&      out_value2;     // Output  port
    sc_signal_bool_vector3&      out_value3;     // Output  port
    sc_signal_bool_vector3&      out_value4;     // Output  port
    sc_signal<bool>&             out_valid;                         // Output  port
    const sc_signal<bool>&       in_ack;

    //
    // Constructor
    //

    stimulus(
        sc_module_name    NAME,      // reference name
        sc_clock&      CLK,          // clock
        sc_signal<bool>& RESET,
        sc_signal_bool_vector2&            OUT_VALUE1,
        sc_signal_bool_vector2&            OUT_VALUE2,
        sc_signal_bool_vector3&            OUT_VALUE3,
        sc_signal_bool_vector3&            OUT_VALUE4,
        sc_signal<bool>&                   OUT_VALID,
        const sc_signal<bool>&             IN_ACK
        )
        :
          reset        (RESET),
          out_value1    (OUT_VALUE1),
          out_value2    (OUT_VALUE2),
          out_value3    (OUT_VALUE3),
          out_value4    (OUT_VALUE4),
          out_valid     (OUT_VALID),
          in_ack        (IN_ACK)
   {
     clk          (CLK);
	 SC_CTHREAD( entry, clk.pos() );
   };
  void entry();
};
// EOF