tlm/examples/tlm_elastic_slave_with_l2.py

74 # Create a system with a Crossbar and an Elastic Trace Player as CPU:
77 system = System(cpu=TraceCPU(cpu_id=0),
83 system.voltage_domain = VoltageDomain()
85 # Create a source clock for the system. This is used as the clock period for
87 system.clk_domain = SrcClockDomain(clock =  '1GHz',
88         voltage_domain = system.voltage_domain)
91 system.cpu_voltage_domain = VoltageDomain()
95 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
96         voltage_domain = system.cpu_voltage_domain)
99 system.cpu.createInterruptController()
100 system.cpu.icache = L1_ICache(size="32kB")
101 system.cpu.dcache = L1_DCache(size="32kB")
102 system.cpu.icache.cpu_side = system.cpu.icache_port
103 system.cpu.dcache.cpu_side = system.cpu.dcache_port
106 system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
107 system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
110 system.tol2bus = L2XBar()
111 system.l2cache = L2Cache(size="1MB")
112 system.physmem = SimpleMemory() # This must be instantiated, even if not needed
115 system.tlm = ExternalSlave()
116 system.tlm.addr_ranges = [AddrRange('4096MB')]
117 system.tlm.port_type = "tlm_slave"
118 system.tlm.port_data = "transactor1"
121 system.membus = SystemXBar()
122 system.system_port = system.membus.slave
123 system.cpu.icache.mem_side = system.tol2bus.slave
124 system.cpu.dcache.mem_side = system.tol2bus.slave
125 system.tol2bus.master = system.l2cache.cpu_side
126 system.l2cache.mem_side = system.membus.slave
127 system.membus.master = system.tlm.port
130 root = Root(full_system = False, system = system)
131 root.system.mem_mode = 'timing'