tlm/conf/tlm_elastic_slave.py

67 # Create a system with a Crossbar and an Elastic Trace Player as CPU:
70 system = System(cpu=TraceCPU(cpu_id=0),
76 system.voltage_domain = VoltageDomain()
78 # Create a source clock for the system. This is used as the clock period for
80 system.clk_domain = SrcClockDomain(clock =  '1GHz',
81         voltage_domain = system.voltage_domain)
84 system.cpu_voltage_domain = VoltageDomain()
88 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
89         voltage_domain = system.cpu_voltage_domain)
92 system.cpu.createInterruptController()
93 system.cpu.icache = L1_ICache(size="32kB")
94 system.cpu.dcache = L1_DCache(size="32kB")
95 system.cpu.icache.cpu_side = system.cpu.icache_port
96 system.cpu.dcache.cpu_side = system.cpu.dcache_port
99 system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
100 system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
103 system.membus = IOXBar(width = 16)
104 system.physmem = SimpleMemory() # This must be instantiated, even if not needed
107 system.tlm = ExternalSlave()
108 system.tlm.addr_ranges = [AddrRange('512MB')]
109 system.tlm.port_type = "tlm_slave"
110 system.tlm.port_data = "transactor"
113 system.membus = SystemXBar()
114 system.system_port = system.membus.slave
115 system.cpu.icache.mem_side = system.membus.slave
116 system.cpu.dcache.mem_side = system.membus.slave
117 system.membus.master = system.tlm.port
120 root = Root(full_system = False, system = system)
121 root.system.mem_mode = 'timing'