src/mem/dram_ctrl.cc

834     // time we need to issue a column command to be seamless
898                     // col-to-col command requirements
987     // Respect the row-to-column command delay for both read and write cmds
1145     // respect any constraints on the command (e.g. tRCD or tCCD)
1150     // the command; need minimum of tBURST between commands
1268     // DRAMPower trace command to be written
1272     MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD :
1275     // Update bus state to reflect when previous command was issued
1281     dram_pkt->rankRef.cmdList.push_back(Command(command, dram_pkt->bank,
1290         // if auto-precharge push a PRE command at the correct tick to the
1458                 // If we are changing command type, incorporate the minimum
1540             // If we are changing command type, incorporate the minimum
1663     // Find command with optimal bank timing
1825              // next_iter references the 1st command after curTick
2118         // push command to DRAMPower
2254         // counter should be one for refresh command only
2296                 // ensure refresh is restarted only after final PRE command.