Lines Matching refs:__SINIC_VAL32
37 #define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
91 __SINIC_VAL32(Config_ZeroCopy, 12, 1) // enable zero copy
92 __SINIC_VAL32(Config_DelayCopy,11, 1) // enable delayed copy
93 __SINIC_VAL32(Config_RSS, 10, 1) // enable receive side scaling
94 __SINIC_VAL32(Config_RxThread, 9, 1) // enable receive threads
95 __SINIC_VAL32(Config_TxThread, 8, 1) // enable transmit thread
96 __SINIC_VAL32(Config_Filter, 7, 1) // enable receive filter
97 __SINIC_VAL32(Config_Vlan, 6, 1) // enable vlan tagging
98 __SINIC_VAL32(Config_Vaddr, 5, 1) // enable virtual addressing
99 __SINIC_VAL32(Config_Desc, 4, 1) // enable tx/rx descriptors
100 __SINIC_VAL32(Config_Poll, 3, 1) // enable polling
101 __SINIC_VAL32(Config_IntEn, 2, 1) // enable interrupts
102 __SINIC_VAL32(Config_TxEn, 1, 1) // enable transmit
103 __SINIC_VAL32(Config_RxEn, 0, 1) // enable receive
106 __SINIC_VAL32(Command_Intr, 1, 1) // software interrupt
107 __SINIC_VAL32(Command_Reset, 0, 1) // reset chip
110 __SINIC_VAL32(Intr_Soft, 8, 1) // software interrupt
111 __SINIC_VAL32(Intr_TxLow, 7, 1) // tx fifo dropped below watermark
112 __SINIC_VAL32(Intr_TxFull, 6, 1) // tx fifo full
113 __SINIC_VAL32(Intr_TxDMA, 5, 1) // tx dma completed w/ interrupt
114 __SINIC_VAL32(Intr_TxPacket, 4, 1) // packet transmitted
115 __SINIC_VAL32(Intr_RxHigh, 3, 1) // rx fifo above high watermark
116 __SINIC_VAL32(Intr_RxEmpty, 2, 1) // rx fifo empty
117 __SINIC_VAL32(Intr_RxDMA, 1, 1) // rx dma completed w/ interrupt
118 __SINIC_VAL32(Intr_RxPacket, 0, 1) // packet received