dev/arm/smmu_v3_transl.cc

111     request = req;
129     beginTransaction(request);
131     smmu.runProcessTiming(this, request.pkt);
139     // But we need to wait for request data esp. in atomic mode.
145     const Addr next4k = (request.addr + 0x1000ULL) & ~0xfffULL;
147     if ((request.addr + request.size) > next4k)
149                 request.addr, request.size);
152     unsigned numSlaveBeats = request.isWrite ?
153         (request.size + (ifc.portWidth - 1)) / ifc.portWidth : 1;
165         completeTransaction(yield, bypass(request.addr));
172     if (request.isPrefetch) {
280             tr = translateStage1And2(yield, request.addr);
282             tr = translateStage2(yield, request.addr, true);
284             tr = bypass(request.addr);
318         ifc.microTLB->lookup(request.sid, request.ssid, request.addr);
323             request.addr, request.sid, request.ssid);
330         request.addr, e->vaMask, request.sid, request.ssid, e->pa);
333     tr.addr = e->pa + (request.addr & ~e->vaMask);;
350         ifc.mainTLB->lookup(request.sid, request.ssid, request.addr);
356                 request.addr, request.sid, request.ssid);
363             "paddr=%#x\n", request.addr, e->vaMask, request.sid,
364             request.ssid, e->pa);
367     tr.addr = e->pa + (request.addr & ~e->vaMask);;
384         smmu.tlb.lookup(request.addr, context.asid, context.vmid);
389             request.addr, context.asid, context.vmid);
396             request.addr, e->vaMask, context.asid, context.vmid, e->pa);
399     tr.addr = e->pa + (request.addr & ~e->vaMask);;
418     e.sid = request.sid;
419     e.ssid = request.ssid;
421     e.va = request.addr & e.vaMask;
449     e.prefetched = request.isPrefetch;
450     e.sid = request.sid;
451     e.ssid = request.ssid;
453     e.va = request.addr & e.vaMask;
461         alloc = request.isPrefetch ?
487     e.va = request.addr & e.vaMask;
513         smmu.configCache.lookup(request.sid, request.ssid);
518                 request.sid, request.ssid);
524             request.sid, request.ssid, e->ttb0, e->asid);
553     e.sid = request.sid;
554     e.ssid = request.ssid;
585     doReadSTE(yield, ste, request.sid);
628         doReadCD(yield, cd, ste, request.sid, request.ssid);
765         if (valid && leaf && request.isWrite &&
849         if (valid && leaf && request.isWrite &&
1044     Addr addr4k = request.addr & ~0xfffULL;
1050         Addr other4k = (*it)->request.addr & ~0xfffULL;
1062             this, request.addr & ~0xfffULL);
1070     Addr addr4k = request.addr & ~0xfffULL;
1081             Addr other4k = (*it)->request.addr & ~0xfffULL;
1109             this, request.addr & ~0xfffULL);
1118         panic("hazard4kRelease: request not found");
1128     auto orderId = AMBA::orderId(request.pkt);
1135         request.isWrite ?
1143     auto orderId = AMBA::orderId(request.pkt);
1148         request.isWrite ?
1161             if (AMBA::orderId((*it)->request.pkt) == orderId) {
1182     auto orderId = AMBA::orderId(request.pkt);
1187         request.isWrite ?
1197         panic("hazardIdRelease: request not found");
1218             SMMUTranslRequest::prefetch(addr, request.sid, request.ssid));
1228     unsigned numMasterBeats = request.isWrite ?
1229         (request.size + (smmu.masterPortWidth-1))
1240     if (!request.isAtsRequest && request.isWrite)
1242             (request.size + (ifc.portWidth-1)) / ifc.portWidth;
1249     if (request.isAtsRequest) {
1253             request.pkt->makeAtomicResponse();
1255             request.pkt->makeTimingResponse();
1264     a.pkt = request.pkt;
1272     if (!request.isAtsRequest) {
1274         pkt->setAddr(request.addr);