Lines Matching refs:Addr
66 SMMUTranslRequest::prefetch(Addr addr, uint32_t sid, uint32_t ssid)
145 const Addr next4k = (request.addr + 0x1000ULL) & ~0xfffULL;
236 SMMUTranslationProcess::bypass(Addr addr) const
650 Addr addr, uint16_t asid, uint16_t vmid,
688 SMMUTranslationProcess::walkCacheUpdate(Yield &yield, Addr va,
689 Addr vaMask, Addr pa,
729 SMMUTranslationProcess::walkStage1And2(Yield &yield, Addr addr,
731 unsigned level, Addr walkPtr)
740 Addr pte_addr = walkPtr + pt_ops->index(addr, level);
813 SMMUTranslationProcess::walkStage2(Yield &yield, Addr addr, bool final_tr,
815 unsigned level, Addr walkPtr)
824 Addr pte_addr = walkPtr + pt_ops->index(addr, level);
879 SMMUTranslationProcess::translateStage1And2(Yield &yield, Addr addr)
914 Addr table_addr = context.ttb0;
935 SMMUTranslationProcess::translateStage2(Yield &yield, Addr addr, bool final_tr)
1044 Addr addr4k = request.addr & ~0xfffULL;
1050 Addr other4k = (*it)->request.addr & ~0xfffULL;
1070 Addr addr4k = request.addr & ~0xfffULL;
1081 Addr other4k = (*it)->request.addr & ~0xfffULL;
1205 SMMUTranslationProcess::issuePrefetch(Addr addr)
1306 Addr event_addr =
1336 Addr ste_addr;
1400 Addr cd_addr;
1459 SMMUTranslationProcess::doReadConfig(Yield &yield, Addr addr,
1467 SMMUTranslationProcess::doReadPTE(Yield &yield, Addr va, Addr addr,
1473 Addr mask = pte_size - 1;
1474 Addr base = addr & ~mask;