dev/arm/smmu_v3_transl.cc

584     StreamTableEntry ste;
585     doReadSTE(yield, ste, request.sid);
587     switch (ste.dw0.config) {
606                 ste.dw0.config);
613         tc.httb = ste.dw3.s2ttb << STE_S2TTB_SHIFT;
614         tc.vmid = ste.dw2.s2vmid;
615         tc.stage2TranslGranule = ste.dw2.s2tg;
616         tc.s2t0sz = ste.dw2.s2t0sz;
628         doReadCD(yield, cd, ste, request.sid, request.ssid);
1329                                   StreamTableEntry &ste,
1365         ste_addr = (l2_ptr & ST_L2_ADDR_MASK) + index * sizeof(ste);
1370             (smmu.regs.strtab_base & VMT_BASE_ADDR_MASK) + sid * sizeof(ste);
1377     doReadConfig(yield, ste_addr, &ste, sizeof(ste), sid, 0);
1379     DPRINTF(SMMUv3, "Got STE at %#x [0]: 0x%016x\n", ste_addr, ste.dw0);
1380     DPRINTF(SMMUv3, "    STE at %#x [1]: 0x%016x\n", ste_addr, ste.dw1);
1381     DPRINTF(SMMUv3, "    STE at %#x [2]: 0x%016x\n", ste_addr, ste.dw2);
1382     DPRINTF(SMMUv3, "    STE at %#x [3]: 0x%016x\n", ste_addr, ste.dw3);
1383     DPRINTF(SMMUv3, "    STE at %#x [4]: 0x%016x\n", ste_addr, ste._pad[0]);
1384     DPRINTF(SMMUv3, "    STE at %#x [5]: 0x%016x\n", ste_addr, ste._pad[1]);
1385     DPRINTF(SMMUv3, "    STE at %#x [6]: 0x%016x\n", ste_addr, ste._pad[2]);
1386     DPRINTF(SMMUv3, "    STE at %#x [7]: 0x%016x\n", ste_addr, ste._pad[3]);
1388     if (!ste.dw0.valid)
1397                                  const StreamTableEntry &ste,
1402     if (ste.dw0.s1cdmax == 0) {
1403         cd_addr = ste.dw0.s1ctxptr << ST_CD_ADDR_SHIFT;
1405         unsigned max_ssid = 1 << ste.dw0.s1cdmax;
1409         if (ste.dw0.s1fmt==STAGE1_CFG_2L_4K ||
1410             ste.dw0.s1fmt==STAGE1_CFG_2L_64K)
1412             unsigned split = ste.dw0.s1fmt==STAGE1_CFG_2L_4K ? 7 : 11;
1415             uint64_t l2_addr = (ste.dw0.s1ctxptr << ST_CD_ADDR_SHIFT) +
1430         } else if (ste.dw0.s1fmt == STAGE1_CFG_1L) {
1431             cd_addr = (ste.dw0.s1ctxptr << ST_CD_ADDR_SHIFT) + ssid*sizeof(cd);