dev/arm/smmu_v3_transl.cc

52     req.addr         = pkt->getAddr();
66 SMMUTranslRequest::prefetch(Addr addr, uint32_t sid, uint32_t ssid)
69     req.addr         = addr;
145     const Addr next4k = (request.addr + 0x1000ULL) & ~0xfffULL;
147     if ((request.addr + request.size) > next4k)
148         panic("Transaction crosses 4k boundary (addr=%#x size=%#x)!\n",
149                 request.addr, request.size);
165         completeTransaction(yield, bypass(request.addr));
236 SMMUTranslationProcess::bypass(Addr addr) const
240     tr.addr = addr;
280             tr = translateStage1And2(yield, request.addr);
282             tr = translateStage2(yield, request.addr, true);
284             tr = bypass(request.addr);
318         ifc.microTLB->lookup(request.sid, request.ssid, request.addr);
323             request.addr, request.sid, request.ssid);
330         request.addr, e->vaMask, request.sid, request.ssid, e->pa);
333     tr.addr = e->pa + (request.addr & ~e->vaMask);;
350         ifc.mainTLB->lookup(request.sid, request.ssid, request.addr);
356                 request.addr, request.sid, request.ssid);
363             "paddr=%#x\n", request.addr, e->vaMask, request.sid,
367     tr.addr = e->pa + (request.addr & ~e->vaMask);;
384         smmu.tlb.lookup(request.addr, context.asid, context.vmid);
389             request.addr, context.asid, context.vmid);
396             request.addr, e->vaMask, context.asid, context.vmid, e->pa);
399     tr.addr = e->pa + (request.addr & ~e->vaMask);;
421     e.va = request.addr & e.vaMask;
422     e.pa = tr.addr & e.vaMask;
453     e.va = request.addr & e.vaMask;
454     e.pa = tr.addr & e.vaMask;
487     e.va = request.addr & e.vaMask;
490     e.pa = tr.addr & e.vaMask;
650         Addr addr, uint16_t asid, uint16_t vmid,
670         walkEntry = smmu.walkCache.lookup(addr, pt_ops->walkMask(level),
676                     indent, addr, asid, vmid, walkEntry->pa, stage, level);
680                     indent, addr, asid, vmid, stage, level);
729 SMMUTranslationProcess::walkStage1And2(Yield &yield, Addr addr,
740         Addr pte_addr = walkPtr + pt_ops->index(addr, level);
745         doReadPTE(yield, addr, pte_addr, &pte, 1, level);
785             walkPtr = s2tr.addr;
788         walkCacheUpdate(yield, addr, pt_ops->walkMask(level), walkPtr,
795     tr.addr     = walkPtr + (addr & ~tr.addrMask);
799         TranslResult s2tr = translateStage2(yield, tr.addr, true);
806     walkCacheUpdate(yield, addr, tr.addrMask, tr.addr,
813 SMMUTranslationProcess::walkStage2(Yield &yield, Addr addr, bool final_tr,
824         Addr pte_addr = walkPtr + pt_ops->index(addr, level);
829         doReadPTE(yield, addr, pte_addr, &pte, 2, level);
862             walkCacheUpdate(yield, addr, pt_ops->walkMask(level), walkPtr,
872     tr.addr     = walkPtr + (addr & ~tr.addrMask);
879 SMMUTranslationProcess::translateStage1And2(Yield &yield, Addr addr)
893         walkCacheLookup(yield, walk_ep, addr,
907             tr.addr     = walk_ep->pa + (addr & ~walk_ep->vaMask);
911             tr = walkStage1And2(yield, addr, pt_ops, level+1, walk_ep->pa);
920             table_addr = s2tr.addr;
923         tr = walkStage1And2(yield, addr, pt_ops,
929         DPRINTF(SMMUv3, "Translated vaddr %#x to paddr %#x\n", addr, tr.addr);
935 SMMUTranslationProcess::translateStage2(Yield &yield, Addr addr, bool final_tr)
944         ipa_ep = smmu.ipaCache.lookup(addr, context.vmid);
951         tr.addr     = ipa_ep->pa + (addr & ~ipa_ep->ipaMask);
956             addr, context.vmid, tr.addr);
961                 addr, context.vmid);
974             walkCacheLookup(yield, walk_ep, addr,
989             tr.addr     = walk_ep->pa + (addr & ~walk_ep->vaMask);
993             tr = walkStage2(yield, addr, final_tr, pt_ops,
997         tr = walkStage2(yield, addr, final_tr, pt_ops,
1004             context.stage1Enable ? "ip" : "v", addr, tr.addr);
1010         e.ipa = addr & e.ipaMask;
1011         e.pa = tr.addr & tr.addrMask;
1034     tr.addr     = s2tr.addr;
1044     Addr addr4k = request.addr & ~0xfffULL;
1050         Addr other4k = (*it)->request.addr & ~0xfffULL;
1062             this, request.addr & ~0xfffULL);
1070     Addr addr4k = request.addr & ~0xfffULL;
1081             Addr other4k = (*it)->request.addr & ~0xfffULL;
1109             this, request.addr & ~0xfffULL);
1205 SMMUTranslationProcess::issuePrefetch(Addr addr)
1218             SMMUTranslRequest::prefetch(addr, request.sid, request.ssid));
1267     a.pkt->setAddr(tr.addr);
1268     a.pkt->req->setPaddr(tr.addr);
1274         pkt->setAddr(request.addr);
1310     DPRINTF(SMMUv3, "Sending event to addr=%#08x (pos=%d): type=%#x stag=%#x "
1419                 l2_addr = translateStage2(yield, l2_addr, false).addr;
1436         cd_addr = translateStage2(yield, cd_addr, false).addr;
1459 SMMUTranslationProcess::doReadConfig(Yield &yield, Addr addr,
1463     doRead(yield, addr, ptr, size);
1467 SMMUTranslationProcess::doReadPTE(Yield &yield, Addr va, Addr addr,
1474     Addr base = addr & ~mask;