dev/arm/gic_v3_cpu_interface.cc

61     hppi.prio = 0xff;
62     hppi.intid = Gicv3::INTID_SPURIOUS;
75     if (intid == hppi.intid)
76         hppi.prio = 0xff;
403                   activateIRQ(int_id, hppi.group);
459                   activateIRQ(int_id, hppi.group);
1650     if (hppi.prio == 0xff || !groupEnabled(hppi.group)) {
1654     bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS;
1656     if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
1661     if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon())
1670     return hppi.intid;
1676     if (hppi.prio == 0xff || !groupEnabled(hppi.group)) {
1682         if (hppi.group == Gicv3::G0S) {
1684         } else if (hppi.group == Gicv3::G1NS) {
1689     if (hppi.group == Gicv3::G0S) {
1693     bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS);
1705     return hppi.intid;
1815     uint32_t prio = hppi.prio & 0xf8;
2032     if (hppi.group == Gicv3::G1S && !haveEL(EL3)) {
2037         hppi.group = Gicv3::G0S;
2041         ArmISA::InterruptTypes int_type = intSignalType(hppi.group);
2252     if (hppi.prio == 0xff) {
2257     if (!groupEnabled(hppi.group)) {
2262     if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) {
2273     uint32_t prio_mask = groupPriorityMask(hppi.group);
2275     if ((hppi.prio & prio_mask) < (rprio & prio_mask)) {
2578     SERIALIZE_SCALAR(hppi.intid);
2579     SERIALIZE_SCALAR(hppi.prio);
2580     SERIALIZE_ENUM(hppi.group);
2586     UNSERIALIZE_SCALAR(hppi.intid);
2587     UNSERIALIZE_SCALAR(hppi.prio);
2588     UNSERIALIZE_ENUM(hppi.group);