dev/arm/gic_v3_cpu_interface.cc

734 Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
738             miscRegName[misc_reg], val);
747             return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val);
750         setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val);
770             return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val);
792               return setMiscReg(MISCREG_ICV_EOIR0_EL1, val);
795           int int_id = val & 0xffffff;
820           int int_id = val & 0xffffff;
862               return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
865           int int_id = val & 0xffffff;
899           int int_id = val & 0xffffff;
941               return setMiscReg(MISCREG_ICV_DIR_EL1, val);
944           int int_id = val & 0xffffff;
1021           int int_id = val & 0xffffff;
1050             return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
1058             return setMiscReg(MISCREG_ICV_BPR1_EL1, val);
1061         val &= 0x7;
1068             val = val > GIC_MIN_BPR ? val : GIC_MIN_BPR;
1070                 isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val);
1072                 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S, val);
1080             val = val > GIC_MIN_BPR_NS ? val : GIC_MIN_BPR_NS;
1084                 isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val);
1112           if (val < min_VPBR) {
1113               val = min_VPBR;
1117               ich_vmcr_el2.VBPR0 = val;
1119               ich_vmcr_el2.VBPR1 = val;
1131               return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
1142           ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
1208          ICV_CTLR_EL1 requested_icv_ctlr_el1 = val;
1213          val = icv_ctlr_el1;
1239           ICC_CTLR_EL3 requested_icc_ctlr_el3 = val;
1275           val = icc_ctlr_el3;
1283               return setMiscReg(MISCREG_ICV_PMR_EL1, val);
1286           val &= 0xff;
1306               val = (val >> 1) | 0x80;
1309           val &= ~0U << (8 - PRIORITY_BITS);
1316           ich_vmcr_el2.VPMR = val & 0xff;
1327               return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
1330           isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val);
1337           bool enable = val & 0x1;
1350               return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
1353           setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
1360           bool enable = val & 0x1;
1372           ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
1385         generateSGI(val, Gicv3::G0S);
1393         generateSGI(val, group);
1402         generateSGI(val, group);
1421         ICH_HCR_EL2 requested_ich_hcr_el2 = val;
1446         val = ich_hcr_el2;
1454         ICH_LRC requested_ich_lrc = val;
1483         val = ich_lrc;
1492           val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
1499           ICH_LR_EL2 requested_ich_lr_el2 = val;
1534           val = ich_lr_el2;
1542           ICH_VMCR_EL2 requested_ich_vmcr_el2 = val;
1566           val = ich_vmcr_el2;
1609     isa->setMiscRegNoEffect(misc_reg, val);
1624 Gicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const
1627         isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()), val);
1768 Gicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group)
1770     uint8_t aff3 = bits(val, 55, 48);
1771     uint8_t aff2 = bits(val, 39, 32);
1772     uint8_t aff1 = bits(val, 23, 16);;
1773     uint16_t target_list = bits(val, 15, 0);
1774     uint32_t int_id = bits(val, 27, 24);
1775     bool irm = bits(val, 40, 40);
1776     uint8_t rs = bits(val, 47, 44);