dev/arm/gic_v2.cc

143     const ContextID ctx = pkt->req->contextId();
147     const uint32_t resp = readDistributor(ctx, daddr, pkt->getSize());
169 GicV2::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz)
174         return getIntGroup(ctx, ix);
180         return getIntEnabled(ctx, ix);
186         return getIntEnabled(ctx, ix);
192         return getPendingInt(ctx, ix);
198         return getPendingInt(ctx, ix);
204         return getActiveInt(ctx, ix);
210         return getActiveInt(ctx, ix);
222             return getIntPriority(ctx, int_num);
225             return (getIntPriority(ctx, int_num) |
226                     getIntPriority(ctx, int_num+1) << 8);
229             return (getIntPriority(ctx, int_num) |
230                     getIntPriority(ctx, int_num+1) << 8 |
231                     getIntPriority(ctx, int_num+2) << 16 |
232                     getIntPriority(ctx, int_num+3) << 24);
243             return getCpuTarget(ctx, int_num);
247             return (getCpuTarget(ctx, int_num) |
248                     getCpuTarget(ctx, int_num+1) << 8 |
249                     getCpuTarget(ctx, int_num+2) << 16 |
250                     getCpuTarget(ctx, int_num+3) << 24) ;
296     const ContextID ctx = pkt->req->contextId();
297     assert(ctx < sys->numRunningContexts());
300             ctx);
302     pkt->setLE<uint32_t>(readCpu(ctx, daddr));
309 GicV2::readCpu(ContextID ctx, Addr daddr)
315         return cpuControl[ctx];
317         return cpuPriority[ctx];
319         return cpuBpr[ctx];
321         if (enabled && cpuEnabled(ctx)) {
322             int active_int = cpuHighestInt[ctx];
336                         if (cpugen & (1 << ctx)) {
341                     uint64_t sgi_num = ULL(1) << (ctx + 8 * iar.cpu_id);
346                     cpuSgiActiveExt[ctx] |= sgi_num;
347                     cpuSgiPendingExt[ctx] &= ~sgi_num;
350                 uint32_t int_num = 1 << (cpuHighestInt[ctx] - SGI_MAX);
351                 cpuPpiActive[ctx] |= int_num;
353                 cpuPpiPending[ctx] &= ~int_num;
356                 uint32_t int_num = 1 << intNumToBit(cpuHighestInt[ctx]);
357                 getActiveInt(ctx, intNumToWord(cpuHighestInt[ctx])) |= int_num;
359                 if (!isLevelSensitive(ctx, active_int)) {
360                     getPendingInt(ctx, intNumToWord(cpuHighestInt[ctx]))
367                     ctx, iar.ack_id, iar.cpu_id, iar);
368             cpuHighestInt[ctx] = SPURIOUS_INT;
370             clearInt(ctx, active_int);
394     const ContextID ctx = pkt->req->contextId();
417     writeDistributor(ctx, daddr, pkt_data, data_sz);
424 GicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data,
430         getIntGroup(ctx, ix) |= data;
437         getIntEnabled(ctx, ix) |= data;
444         getIntEnabled(ctx, ix) &= ~data;
452         getPendingInt(ctx, ix) |= mask;
461         getPendingInt(ctx, ix) &= ~mask;
468         getActiveInt(ctx, ix) |= data;
474         getActiveInt(ctx, ix) &= ~data;
482             getIntPriority(ctx, int_num) = data;
485             getIntPriority(ctx, int_num) = bits(data, 7, 0);
486             getIntPriority(ctx, int_num + 1) = bits(data, 15, 8);
490             getIntPriority(ctx, int_num) = bits(data, 7, 0);
491             getIntPriority(ctx, int_num + 1) = bits(data, 15, 8);
492             getIntPriority(ctx, int_num + 2) = bits(data, 23, 16);
493             getIntPriority(ctx, int_num + 3) = bits(data, 31, 24);
549         softInt(ctx, data);
563     const ContextID ctx = pkt->req->contextId();
567             ctx, daddr, data);
569     writeCpu(ctx, daddr, data);
576 GicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
580         cpuControl[ctx] = data;
583         cpuPriority[ctx] = data;
589         cpuBpr[ctx] = bpr;
596             uint64_t clr_int = ULL(1) << (ctx + 8 * iar.cpu_id);
598                 !(cpuSgiActiveExt[ctx] & (1 << iar.ack_id)))
601                 cpuSgiActiveExt[ctx] &= ~(1 << iar.ack_id);
606             if (!(cpuPpiActive[ctx] & int_num))
608                       "that isn't active?\n", ctx);
609             cpuPpiActive[ctx] &= ~int_num;
612             if (!(getActiveInt(ctx, intNumToWord(iar.ack_id)) & int_num))
615             getActiveInt(ctx, intNumToWord(iar.ack_id)) &= ~int_num;
619                 ctx, iar.ack_id, iar.cpu_id);
635     if (cpuEnabled(ctx)) updateIntState(-1);
639 GicV2::getBankedRegs(ContextID ctx) {
640     if (bankedRegs.size() <= ctx)
641         bankedRegs.resize(ctx + 1);
643     if (!bankedRegs[ctx])
644         bankedRegs[ctx] = new BankedRegs;
645     return *bankedRegs[ctx];
649 GicV2::softInt(ContextID ctx, SWI swi)
657                     ctx, dest);
678                     ctx, ctx);
679             if (cpuEnabled(ctx)) {
680                 cpuSgiPendingExt[ctx] |= (1 << swi.sgi_id);
681                 DPRINTF(IPI, "SGI[%d]=%#x\n", ctx,
682                         cpuSgiPendingExt[ctx]);
698             swi.cpu_list = 1 << ctx;
703         DPRINTF(IPI, "Generating softIRQ from CPU %d for %#x\n", ctx,
710                 cpuSgiPending[swi.sgi_id] |= (1 << i) << (8 * ctx);
916 GicV2::clearInt(ContextID ctx, uint32_t int_num)
918     if (isFiq(ctx, int_num)) {
919         platform->intrctrl->clear(ctx, ArmISA::INT_FIQ, 0);
921         platform->intrctrl->clear(ctx, ArmISA::INT_IRQ, 0);