dev/arm/gic_v2.cc

54 const AddrRange GicV2::GICD_IGROUPR   (0x080, 0x0ff);
55 const AddrRange GicV2::GICD_ISENABLER (0x100, 0x17f);
56 const AddrRange GicV2::GICD_ICENABLER (0x180, 0x1ff);
57 const AddrRange GicV2::GICD_ISPENDR   (0x200, 0x27f);
58 const AddrRange GicV2::GICD_ICPENDR   (0x280, 0x2ff);
59 const AddrRange GicV2::GICD_ISACTIVER (0x300, 0x37f);
60 const AddrRange GicV2::GICD_ICACTIVER (0x380, 0x3ff);
61 const AddrRange GicV2::GICD_IPRIORITYR(0x400, 0x7ff);
62 const AddrRange GicV2::GICD_ITARGETSR (0x800, 0xbff);
63 const AddrRange GicV2::GICD_ICFGR     (0xc00, 0xcff);
65 GicV2::GicV2(const Params *p)
104 GicV2::~GicV2()
113 GicV2::read(PacketPtr pkt)
127 GicV2::write(PacketPtr pkt)
140 GicV2::readDistributor(PacketPtr pkt)
169 GicV2::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz)
291 GicV2::readCpu(PacketPtr pkt)
309 GicV2::readCpu(ContextID ctx, Addr daddr)
389 GicV2::writeDistributor(PacketPtr pkt)
424 GicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data,
558 GicV2::writeCpu(PacketPtr pkt)
576 GicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
638 GicV2::BankedRegs&
639 GicV2::getBankedRegs(ContextID ctx) {
649 GicV2::softInt(ContextID ctx, SWI swi)
719 GicV2::genSwiMask(int cpu)
727 GicV2::getCpuPriority(unsigned cpu)
738 GicV2::updateIntState(int hint)
836 GicV2::updateRunPri()
865 GicV2::sendInt(uint32_t num)
879 GicV2::sendPPInt(uint32_t num, uint32_t cpu)
888 GicV2::clearInt(uint32_t num)
907 GicV2::clearPPInt(uint32_t num, uint32_t cpu)
916 GicV2::clearInt(ContextID ctx, uint32_t int_num)
926 GicV2::postInt(uint32_t cpu, Tick when)
935 GicV2::postDelayedInt(uint32_t cpu)
945 GicV2::postFiq(uint32_t cpu, Tick when)
954 GicV2::postDelayedFiq(uint32_t cpu)
964 GicV2::drain()
975 GicV2::drainResume()
982 GicV2::serialize(CheckpointOut &cp) const
1016 GicV2::BankedRegs::serialize(CheckpointOut &cp) const
1026 GicV2::unserialize(CheckpointIn &cp)
1075 GicV2::BankedRegs::unserialize(CheckpointIn &cp)
1084 GicV2 *
1087     return new GicV2(this);