cpu/o3/lsq.hh

166      * from initiateAcc to resource deallocation at commit or squash.
404          * The request is only added if the mask is empty or if there is at
475         RequestPtr request(int idx = 0) { return _requests.at(idx); }
480             return _requests.at(idx);
486         PacketPtr packet(int idx = 0) { return _packets.at(idx); }
859     { thread.at(tid).commitLoads(youngest_inst); }
865     { thread.at(tid).commitStores(youngest_inst); }
881         thread.at(tid).squash(squashed_num);
890     bool violation(ThreadID tid) { return thread.at(tid).violation(); }
896         return thread.at(tid).getMemDepViolator();
900     int getLoadHead(ThreadID tid) { return thread.at(tid).getLoadHead(); }
906         return thread.at(tid).getLoadHeadSeqNum();
910     int getStoreHead(ThreadID tid) { return thread.at(tid).getStoreHead(); }
916         return thread.at(tid).getStoreHeadSeqNum();
922     int getCount(ThreadID tid) { return thread.at(tid).getCount(); }
927     int numLoads(ThreadID tid) { return thread.at(tid).numLoads(); }
932     int numStores(ThreadID tid) { return thread.at(tid).numStores(); }
991     bool hasStoresToWB(ThreadID tid) { return thread.at(tid).hasStoresToWB(); }
994     int numStoresToWB(ThreadID tid) { return thread.at(tid).numStoresToWB(); }
1001     bool willWB(ThreadID tid) { return thread.at(tid).willWB(); }
1006     void dumpInsts(ThreadID tid) const { thread.at(tid).dumpInsts(); }
1008     /** Executes a read operation, using the load specified at the load
1013     /** Executes a store operation, using the store specified at the store
1075      * can occupy at most.
1125     return thread.at(tid).read(req, load_idx);
1134     return thread.at(tid).write(req, data, store_idx);