arch/arm/process.cc

222     const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
224     hwcap |= (isa_r0.aes >= 1) ? Arm_Aes : 0;
225     hwcap |= (isa_r0.aes >= 2) ? Arm_Pmull : 0;
226     hwcap |= (isa_r0.sha1 >= 1) ? Arm_Sha1 : 0;
227     hwcap |= (isa_r0.sha2 >= 1) ? Arm_Sha2 : 0;
228     hwcap |= (isa_r0.sha2 >= 2) ? Arm_Sha512 : 0;
229     hwcap |= (isa_r0.crc32 >= 1) ? Arm_Crc32 : 0;
230     hwcap |= (isa_r0.atomic >= 1) ? Arm_Atomics : 0;
231     hwcap |= (isa_r0.rdm >= 1) ? Arm_Asimdrdm : 0;
232     hwcap |= (isa_r0.sha3 >= 1) ? Arm_Sha3 : 0;
233     hwcap |= (isa_r0.sm3 >= 1) ? Arm_Sm3 : 0;
234     hwcap |= (isa_r0.sm4 >= 1) ? Arm_Sm4 : 0;
235     hwcap |= (isa_r0.dp >= 1) ? Arm_Asimddp : 0;
236     hwcap |= (isa_r0.fhm >= 1) ? Arm_Asimdfhm : 0;
237     hwcap |= (isa_r0.ts >= 1) ? Arm_Flagm : 0;