Lines Matching refs:newVal
778 RegVal newVal = val;
851 newVal &= cpacrMask;
852 newVal |= old_val & ~cpacrMask;
854 miscRegName[misc_reg], newVal);
866 newVal &= cpacrMask;
868 miscRegName[misc_reg], newVal);
881 newVal &= cptrMask;
889 newVal |= cptrMask;
891 miscRegName[misc_reg], newVal);
904 newVal &= cptrMask;
906 miscRegName[misc_reg], newVal);
945 newVal = (newVal & (uint32_t)fpscrMask) |
948 tc->getDecoderPtr()->setContext(newVal);
966 newVal = (newVal & (uint32_t)fpscrMask) |
983 newVal = (newVal & (uint32_t)fpscrMask) |
991 assert(!(newVal & ~CpsrMaskQ));
992 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
998 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
999 (newVal & FpscrQcMask);
1005 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1006 (newVal & FpscrExcMask);
1015 newVal = (newVal & fpexcMask) |
1030 newVal = newVal & ~ifsrMask;
1037 newVal = newVal & ~dfsrMask;
1047 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1056 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1067 SCTLR new_sctlr = newVal;
1160 mbits(newVal, 31, 12),
1161 bits(newVal, 7,0));
1175 mbits(newVal, 31, 12),
1176 bits(newVal, 7,0));
1189 bits(newVal, 7,0));
1202 bits(newVal, 7,0));
1218 mbits(newVal, 31,12));
1231 mbits(newVal, 31,12));
1247 mbits(newVal, 31,12));
1260 mbits(newVal, 31,12));
1277 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1292 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1305 mbits(newVal, 31, 12),
1306 bits(newVal, 7,0));
1319 mbits(newVal, 31, 12),
1320 bits(newVal, 7,0));
1333 bits(newVal, 7,0));
1346 bits(newVal, 7,0));
1453 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1465 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1479 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1492 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1504 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1505 bits(newVal, 55, 48);
1508 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1520 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1521 bits(newVal, 55, 48);
1524 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1536 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1537 bits(newVal, 55, 48);
1548 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1549 bits(newVal, 55, 48);
1565 static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1578 static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1592 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1606 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1619 pmu->setMiscReg(misc_reg, newVal);
1627 newVal &= ~((uint32_t) hstrMask);
1641 newVal = (newVal & ~mask) | (oldValue & mask);
1745 RegVal newVal;
1750 newVal = (paddr & mask(39, 12)) |
1753 newVal = (paddr & 0xfffff000) |
1758 val, newVal);
1765 newVal = ((fsr >> 9) & 1) << 11;
1766 if (newVal) {
1768 newVal |= ((fsr >> 0) & 0x3f) << 1;
1771 newVal |= ((fsr >> 0) & 0xf) << 1;
1772 newVal |= ((fsr >> 10) & 0x1) << 5;
1773 newVal |= ((fsr >> 12) & 0x1) << 6;
1775 newVal |= 0x1; // F bit
1776 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
1777 newVal |= armFault->isStage2() ? 0x200 : 0;
1780 val, fsr, newVal);
1782 setMiscRegNoEffect(MISCREG_PAR, newVal);
1790 TTBCR ttbcrNew = newVal;
1812 newVal = newVal & ttbcrMask;
1814 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
1830 newVal = (newVal & (~ttbrMask));
1874 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
1875 newVal = cpsr;
1880 tc->setIntReg(INTREG_SP0, newVal);
1883 tc->setIntReg(INTREG_SP1, newVal);
1886 tc->setIntReg(INTREG_SP2, newVal);
1891 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
1892 newVal = cpsr;
1899 cpsr.el = (uint8_t) ((CPSR) newVal).el;
1900 newVal = cpsr;
1910 cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
1911 newVal = cpsr;
2010 RegVal newVal;
2019 newVal = (paddr & mask(47, 12)) | attr;
2022 val, newVal);
2031 newVal = ((fsr >> 9) & 1) << 11;
2033 newVal |= ((fsr >> 0) & 0x3f) << 1;
2034 newVal |= 0x1; // F bit
2035 newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
2036 newVal |= armFault->isStage2() ? 0x200 : 0;
2038 newVal = 1; // F bit
2039 newVal |= fsr << 1; // FST
2041 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
2042 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
2043 newVal |= 1 << 11; // RES1
2047 val, fsr, newVal);
2049 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
2059 newVal = val & spsr_mask;
2075 getGenericTimer(tc).setMiscReg(misc_reg, newVal);
2080 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal);
2090 setMiscRegNoEffect(misc_reg, newVal);