Lines Matching defs:val
437 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
439 if (val & reg.res0()) {
441 miscRegName[misc_reg], val & reg.res0());
443 if ((val & reg.res1()) != reg.res1()) {
445 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
447 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
506 RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
507 val &= cpacrMask;
509 miscRegName[misc_reg], val);
510 return val;
688 RegVal val = readMiscRegNoEffect(misc_reg);
690 val &= ~(1 << 14);
698 val |= (mask ^ 0x7FFF) & 0xBFFF;
701 val |= 0x33FF;
702 return (val);
753 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
761 auto v = (val & ~reg.wi()) | reg.rao();
775 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
778 RegVal newVal = val;
783 updateRegMap(val);
788 CPSR cpsr = val;
820 miscRegName[misc_reg], val);
823 miscRegName[misc_reg], val);
1736 0, val, 0, flags, Request::funcMasterId,
1758 val, newVal);
1780 val, fsr, newVal);
1864 CPSR cpsr = val;
2004 req->setVirt(0, val, 0, flags, Request::funcMasterId,
2022 val, newVal);
2047 val, fsr, newVal);
2059 newVal = val & spsr_mask;
2064 miscRegName[misc_reg], uint32_t(val));