arch/arm/faults.cc

296 ArmFault::getVector(ThreadContext *tc)
301     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
302     assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
303     assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
308         base = tc->readMiscReg(MISCREG_MVBAR);
311         base = tc->readMiscReg(MISCREG_HVBAR);
314         SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
318             base = ArmSystem::haveSecurity(tc) ?
319                 tc->readMiscReg(MISCREG_VBAR) : 0;
324     return base + offset(tc);
328 ArmFault::getVector64(ThreadContext *tc)
333         assert(ArmSystem::haveSecurity(tc));
334         vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
337         assert(ArmSystem::haveVirtualization(tc));
338         vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
341         vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
347     return vbar + offset64(tc);
383 ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
386     uint32_t exc_class = (uint32_t) ec(tc);
389     assert(!from64 || ArmSystem::highestELIs64(tc));
420     tc->setMiscReg(syndrome_reg, value);
424 ArmFault::update(ThreadContext *tc)
426     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
436     if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
439     } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
452     AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
455             const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
459         const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
461             const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
466     to64 = ELIs64(tc, toEL);
474 ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
481     update(tc);
485         invoke64(tc, inst);
491     bool have_security       = ArmSystem::haveSecurity(tc);
493     FaultBase::invoke(tc);
498     SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
499     SCR scr = tc->readMiscReg(MISCREG_SCR);
500     CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
501     saved_cpsr.nz = tc->readCCReg(CCREG_NZ);
502     saved_cpsr.c = tc->readCCReg(CCREG_C);
503     saved_cpsr.v = tc->readCCReg(CCREG_V);
504     saved_cpsr.ge = tc->readCCReg(CCREG_GE);
506     Addr curPc M5_VAR_USED = tc->pcState().pc();
507     ITSTATE it = tc->pcState().itstate();
518         SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
521             tc->setMiscRegNoEffect(MISCREG_SCR, scr);
525     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
530         SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
548         cpsr.a = cpsr.a | abortDisable(tc);
549         cpsr.f = cpsr.f | fiqDisable(tc);
555     tc->setMiscReg(MISCREG_CPSR, cpsr);
558     tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
561     tc->setMiscReg(MISCREG_LOCKFLAG, 0);
564         tc->setMiscReg(MISCREG_ELR_HYP, curPc +
567         tc->setIntReg(INTREG_LR, curPc +
573         tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
576         tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
579         tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
583         tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr);
586         tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
589         tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
590         if (ec(tc) != EC_UNKNOWN)
591             setSyndrome(tc, MISCREG_HSR);
594         assert(ArmSystem::haveVirtualization(tc));
595         tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
596         setSyndrome(tc, MISCREG_HSR);
602     Addr newPc = getVector(tc);
604             "%s\n", name(), cpsr, curPc, tc->readIntReg(INTREG_LR),
615     tc->pcState(pc);
619 ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
629         assert(ArmSystem::haveVirtualization(tc));
634         assert(ArmSystem::haveSecurity(tc));
644     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
646     spsr.nz = tc->readCCReg(CCREG_NZ);
647     spsr.c = tc->readCCReg(CCREG_C);
648     spsr.v = tc->readCCReg(CCREG_V);
658         spsr.ge = tc->readCCReg(CCREG_GE);
659         ITSTATE it = tc->pcState().itstate();
665     tc->setMiscReg(spsr_idx, spsr);
668     Addr curr_pc = tc->pcState().pc();
674     tc->setMiscReg(elr_idx, ret_addr);
676     Addr vec_address = getVector64(tc);
688     tc->setMiscReg(MISCREG_CPSR, cpsr);
696     Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL);
705     tc->pcState(pc);
709         setSyndrome(tc, getSyndromeReg64());
725 Reset::getVector(ThreadContext *tc)
730     CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
731     assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
732     assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
737     base = tc->readMiscReg(MISCREG_MVBAR);
739     return base + offset(tc);
743 Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
746         tc->getCpuPtr()->clearInterrupts(tc->threadId());
747         tc->clearArchRegs();
749     if (!ArmSystem::highestELIs64(tc)) {
750         ArmFault::invoke(tc, inst);
751         tc->setMiscReg(MISCREG_VMPIDR,
752                        getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
755         if (ArmSystem::haveVirtualization(tc) &&
756             !ArmSystem::haveSecurity(tc)) {
757             CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
759             tc->setMiscReg(MISCREG_CPSR, cpsr);
763         PCState pc = ArmSystem::resetAddr(tc);
766         tc->pcState(pc);
771 UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
774         ArmFault::invoke(tc, inst);
794 UndefinedInstruction::routeToHyp(ThreadContext *tc) const
798     SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
799     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
800     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
839 SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
842         ArmFault::invoke(tc, inst);
849     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
852         callNum = tc->readIntReg(INTREG_X8);
854         callNum = tc->readIntReg(INTREG_R7);
856     tc->syscall(callNum, &fault);
859     PCState pc = tc->pcState();
862     tc->pcState(pc);
866 SupervisorCall::routeToHyp(ThreadContext *tc) const
870     SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
871     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
872     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
882 SupervisorCall::ec(ThreadContext *tc) const
905 UndefinedInstruction::ec(ThreadContext *tc) const
921 HypervisorCall::ec(ThreadContext *tc) const
927 HypervisorTrap::ec(ThreadContext *tc) const
934 ArmFaultVals<T>::offset(ThreadContext *tc)
943         CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
945             CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
954 ArmFaultVals<T>::offset64(ThreadContext *tc)
963             if (!inSecureState(tc) && ArmSystem::haveEL(tc, EL2))
964                 lower_32 = ELIs32(tc, EL2);
966                 lower_32 = ELIs32(tc, EL1);
968             lower_32 = ELIs32(tc, static_cast<ExceptionLevel>(toEL - 1));
978 // SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
989 //     tc->setMiscReg(esr_idx, esr);
993 SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
996         ArmFault::invoke(tc, inst);
1002 SecureMonitorCall::ec(ThreadContext *tc) const
1008 SupervisorTrap::routeToHyp(ThreadContext *tc) const
1012     SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1013     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1014     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1017     toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
1032 SupervisorTrap::ec(ThreadContext *tc) const
1041 SecureMonitorTrap::ec(ThreadContext *tc) const
1049 AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1052         tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
1055         if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) {
1058             TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S);
1059             TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS);
1074         tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1077     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1081     ArmFaultVals<T>::invoke(tc, inst);
1084         FSR  fsr  = getFsr(tc);
1086             tc->setMiscReg(T::HFarIndex, faultAddr);
1088             tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
1089             tc->setMiscReg(T::HFarIndex,  OVAddr);
1091             tc->setMiscReg(T::FsrIndex, fsr);
1092             tc->setMiscReg(T::FarIndex, faultAddr);
1102             tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr);
1103             tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4);
1108             tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
1115 AbortFault<T>::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
1117     srcEncoded = getFaultStatusCode(tc);
1121     ArmFault::setSyndrome(tc, syndrome_reg);
1126 AbortFault<T>::getFaultStatusCode(ThreadContext *tc) const
1152 AbortFault<T>::getFsr(ThreadContext *tc) const
1156     auto fsc = getFaultStatusCode(tc);
1177 AbortFault<T>::abortDisable(ThreadContext *tc)
1179     if (ArmSystem::haveSecurity(tc)) {
1180         SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1243 PrefetchAbort::ec(ThreadContext *tc) const
1259         CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1268 PrefetchAbort::routeToMonitor(ThreadContext *tc) const
1272         scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1274         scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1280 PrefetchAbort::routeToHyp(ThreadContext *tc) const
1284     SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1285     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1286     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1287     HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1295              ) && !inSecureState(tc);
1300 DataAbort::ec(ThreadContext *tc) const
1320         CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1329 DataAbort::routeToMonitor(ThreadContext *tc) const
1333         scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1335         scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1341 DataAbort::routeToHyp(ThreadContext *tc) const
1345     SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1346     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1347     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1348     HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1361              ) && !inSecureState(tc);
1422 VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1424     AbortFault<VirtualDataAbort>::invoke(tc, inst);
1425     HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1427     tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
1431 Interrupt::routeToMonitor(ThreadContext *tc) const
1433     assert(ArmSystem::haveSecurity(tc));
1436         scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1438         scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1443 Interrupt::routeToHyp(ThreadContext *tc) const
1447     SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1448     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1449     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1451     toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
1457 Interrupt::abortDisable(ThreadContext *tc)
1459     if (ArmSystem::haveSecurity(tc)) {
1460         SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1470 FastInterrupt::routeToMonitor(ThreadContext *tc) const
1472     assert(ArmSystem::haveSecurity(tc));
1475         scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1477         scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1482 FastInterrupt::routeToHyp(ThreadContext *tc) const
1486     SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1487     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1488     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1490     toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
1496 FastInterrupt::abortDisable(ThreadContext *tc)
1498     if (ArmSystem::haveSecurity(tc)) {
1499         SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1506 FastInterrupt::fiqDisable(ThreadContext *tc)
1508     if (ArmSystem::haveVirtualization(tc)) {
1510     } else if (ArmSystem::haveSecurity(tc)) {
1511         SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1521 PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1523     ArmFaultVals<PCAlignmentFault>::invoke(tc, inst);
1526     tc->setMiscReg(getFaultAddrReg64(), faultPC);
1530 PCAlignmentFault::routeToHyp(ThreadContext *tc) const
1534     SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1535     HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1536     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1539     toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
1550 SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1552     tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1553     ArmFault::invoke(tc, inst);
1557 SystemError::routeToMonitor(ThreadContext *tc) const
1559     assert(ArmSystem::haveSecurity(tc));
1561     SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1566 SystemError::routeToHyp(ThreadContext *tc) const
1571     SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1572     HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1574     toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) ||
1575             (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc));
1585 SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const
1587     const bool have_el2 = ArmSystem::haveVirtualization(tc);
1589     const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1590     const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1592     return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
1597 SoftwareBreakpoint::ec(ThreadContext *tc) const
1603 ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
1611     tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
1612     tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0);