Lines Matching refs:Lphy
154 double Lphy[NUMBER_TECH_FLAVORS];
200 Lphy[0] = 0.12;//Lphy is the physical gate-length. micron
270 Lphy[0] = 0.037;//Lphy is the physical gate-length. micron
315 Lphy[1] = 0.075;
359 Lphy[2] = 0.053;
404 Lphy[3] = 0.12;
449 Lphy[3] = 0.09;
521 Lphy[0] = 0.025;
566 Lphy[1] = 0.045;
610 Lphy[2] = 0.032;
655 Lphy[3] = 0.12;
700 Lphy[3] = 0.065;
770 Lphy[0] = 0.018;
818 Lphy[1] = 0.028;
862 Lphy[2] = 0.022;
907 Lphy[3] = 0.078;
908 Lelec[3] = 0.0504;// Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors.
916 curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0;
952 Lphy[3] = 0.045;
1024 Lphy[0] = 0.013;
1070 Lphy[1] = 0.020;
1114 Lphy[2] = 0.016;
1159 Lphy[3] = 0.056;
1160 Lelec[3] = 0.0419;//Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors.
1168 curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0;
1204 Lphy[3] = 0.032;
1205 Lelec[3] = 0.0205;//Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors.
1275 Lphy[0] = 0.009;//Lphy is the physical gate-length.
1322 Lphy[1] = 0.014;
1366 Lphy[2] = 0.011;
1416 Lphy[3] = 0.022;//micron
1491 Lphy[0] = 0.006;//Lphy is the physical gate-length.
1539 Lphy[3] = 0.022;//micron
1618 g_tp.peri_global.l_phy += curr_alpha * Lphy[peri_global_tech_type];
1634 g_tp.sram_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type];
1654 g_tp.dram_acc.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor];
1665 g_tp.dram_wl.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor];
1680 g_tp.cam_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type];