Lines Matching defs:system
51 # create the system we are going to simulate
52 system = System()
54 system.mem_mode = 'timing'
55 # set the clock fequency of the system
58 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
60 system.cpu = TimingSimpleCPU()
61 # config memory system
62 MemConfig.config_mem(options, system)
64 system.cpu.icache_port = system.membus.slave
65 system.cpu.dcache_port = system.membus.slave
67 system.cpu.createInterruptController()
68 # connect special port in the system to the membus. This port is a
69 # functional-only port to allow the system to read and write memory.
70 system.system_port = system.membus.slave
80 system.cpu.workload = process
82 system.cpu.createThreads()
84 root = Root(full_system=False, system=system)