History log of /gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
Revision Date Author Comments
# 11960:c7bf1b698ccd 29-Mar-2017 Gabe Black <gabeblack@google.com>

stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>


# 11570:4aac82f10951 21-Jul-2016 Curtis Dunham <Curtis.Dunham@arm.com>

stats: update references


# 11103:38f6188421e0 15-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

stats: updates due to recent changesets including d0934b57735a


# 10036:80e84beef3bb 24-Jan-2014 Ali Saidi <Ali.Saidi@ARM.com>

stats: update stats for cache occupancy and clock domain changes


# 9924:31ef410b6843 16-Oct-2013 Steve Reinhardt <steve.reinhardt@amd.com>

test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.


# 9885:afd9ea6101d9 28-Sep-2013 Steve Reinhardt <stever@gmail.com>

tests: update reference outputs

Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes. There are a few stats.txt updates too, but
they are in the minority.


# 9583:c1a5a20cc1fa 11-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

regressions: x86: stats updates due to new x87 insts


# 9481:b0fa6b872f40 24-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.


# 9373:26ba525347fe 30-Dec-2012 Nilay Vaish <nilay@cs.wisc.edu>

x86 regressions: stats update due to new x87 instructions


# 9213:5cab5448909c 11-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

x86 Regressions: Update stats due to register predication


# 9150:a2370fa5c793 15-Aug-2012 Ali Saidi <Ali.Saidi@ARM.com>

stats: Update stats for syscall emulation Linux kernel changes.


# 9096:8971a998190a 09-Jul-2012 Andreas Hansson <andreas.hansson@arm.com>

Stats: Updates due to bus changes

This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.


# 9079:9a244ebdc3c9 29-Jun-2012 Ali Saidi <Ali.Saidi@ARM.com>

Stats: Update stats for RAS and LRU fixes.


# 9055:38f1926fb599 05-Jun-2012 Ali Saidi <saidi@eecs.umich.edu>

all: Update stats for memory per master and total fix.


# 9039:9a22621c741c 04-Jun-2012 Gabe Black <gblack@eecs.umich.edu>

X86: Update stats for the CPUID change.


# 9013:afa278317136 22-May-2012 Nilay Vaish <nilay@cs.wisc.edu>

X86 Regression: update stats due to cc register split


# 8983:8800b05e1cb3 09-May-2012 Nathan Binkert <nate@binkert.org>

stats: update stats for no_value -> nan
Lots of accumulated older changes too.


# 8835:7c68f84d7c4e 12-Feb-2012 Ali Saidi <Ali.Saidi@ARM.com>

stats: update stats for insts/ops and master id changes


# 8802:ef66a9083bc4 28-Jan-2012 Gabe Black <gblack@eecs.umich.edu>

SE/FS: Make both SE and FS tests available all the time.