xref: /gem5/util/tlm/README

This directory contains a demo of a coupling between gem5 and SystemC-TLM.  It
is based on the gem5-systemc implementation in utils/systemc. This Readme gives
an overall overview (I), describes the source files in this directory (II),
explains the build steps (III), shows how to run example simulations (IV-VI)
and lists known issues (VII).


I. Overview
===========

The sources in this directory provide three SystemC modules that manage the
SystemC/gem5 co-simulation: Gem5SimControl, Gem5MasterTransactor, and
Gem5SlaveTransactor. They also implement gem5's ExternalMaster::Port interface
(SCMasterPort) and ExternalSlave::Port interface (SCSlavePort).

**SCMasterPort** and **Gem5MasterTransactor** together form a TLM-to-gem5
bridge. SCMasterPort implements gem5's ExternalMaster::Port interface and forms
the gem5 end of the bridge. Gem5MasterTransactor is a SystemC module that
provides a target socket and represents the TLM side of the bridge. All TLM
requests send to this target socket, are translated to gem5 requests and
forwarded to the gem5 world through the SCMasterPort. Then the gem5 world
handles the request and eventually issues a response. When the response arrives
at the SCMasterPort it gets translated back into a TLM response and forwarded
to the TLM world through target socket of the Gem5MasterTransactor.
SCMasterPort and Gem5MasterTransactor are bound to each other by configuring
them for the same port name.

**SCSlavePort** and **Gem5SlaveTransactor** together form a gem5-to-TLM bridge.
Gem5SlaveTransactor is a SystemC module that provides a initiator socket and
represents the TLM end of the bridge. SCSlavePort implements gem5's
ExternalSlave::Port interface and forms the gem5 side of the bridge. All gem5
requests sent to the SCSlavePort, are translated to TLM requests and forwarded
to the TLM world through the initiator socket of the Gem5SlaveTransactor. Then
the TLM world handles the request and eventually issues a response. When the
response arrives at the Gem5SlaveTransactor it gets translated back into a
gem5 response and forwarded to the gem5 world through the SCSlavePort. SCSLavePort
and Gem5SlaveTransactor are bound to each other by configuring them for the
same port name.

**Gem5SimControl** is the central SystemC module that represents the complete
gem5 world. It is responsible for instantiating all gem5 objects according to a
given configuration file, for configuring the simulation and for maintaining
the gem5 event queue. It also keeps track of all SCMasterPort and SCSlavePort
and responsible for connecting all Gem5MasterTransactor and Gem5SlaveTransactor
modules to their gem5 counterparts. This module must be instantiated exactly
once in order to run a gem5 simulation from within an SystemC environment.


II. Files
=========

    src/sc_slave_port.{cc,hh}     -- Implements SCSlavePort
    src/sc_master_port.{cc,hh}    -- Implements SCMasterPort
    src/sc_mm.{cc,hh}             -- Implementation of a TLM memory manager
    src/sc_ext.{cc,hh}            -- TLM extension that carries a gem5 packet
    src/sc_peq.{cc,hh}            -- TLM PEQ for scheduling gem5 events
    src/sim_control.{cc,hh}       -- Implements Gem5SimControl
    src/slave_transactor.{cc,hh}  -- Implements Gem5SlaveTransactor
    src/master_transactor.{cc,hh} -- Implements Gem5MasterTransactor

    examples/common/cli_parser.{cc,hh}     -- Simple cli argument parser
    examples/common/report_hanlder.{cc,hh} -- Custom SystemC report handler

    examples/slave_port/main.cc           -- demonstration of the slave port
    examples/slave_port/sc_target.{cc,hh} -- an example TLM LT/AT memory module

    examples/master_port/main.cc          -- demonstration of the master port
    examples/master_port/traffic_generator.{cc/hh}
                                         -- an example traffic generator module

    conf/tlm_slave.py           -- simple gem5 configuration connecting to a
                                   SytemC/TLM slave module
    conf/tlm_elastic_slave.py   -- gem5 configuration with an elastic trace
                                   replayer
    conf/tlm_master.py          -- simple gem5 configuration connecting to a
                                   SytemC/TLM master module
    conf/tgen.cfg               -- trace generator configuration

Other Files will be used from utils/systemc example:

    sc_logger.{cc,hh},
    sc_module.{cc,hh},
    sc_gem5_control.{cc,hh},
    stats.{cc,hh}


III. Build
==========

First build a normal gem5 (cxx-config not needed, Python needed).
Second build gem5 as a library with cxx-config support and (optionally)
without python.

> cd ../..
> scons build/ARM/gem5.opt
> scons --with-cxx-config --without-python --without-tcmalloc \
>       build/ARM/libgem5_opt.so
> cd util/tlm

Note: For MAC / OSX this command should be used:
> scons --with-cxx-config --without-python --without-tcmalloc \
>       build/ARM/libgem5_opt.dylib

To build all sources of the SystemC binding and the examples simply run scons:

> scons


IV. Simple Examples
===================

In order to run our example simulation, we first need to create a config.ini
that represents the gem5 configuration. We do so by starting gem5 with the
desired python configuration script.

> ../../build/ARM/gem5.opt conf/tlm_{master,slave}.py

The message "fatal: Can't find port handler type 'tlm_{master,slave}'" is okay.
The configuration will be stored in the m5out/ directory

The build step creates a binary 'gem5.sc' for each example in the
build/examples/{master|slave}_port directories. It can now be used to load in
the generated configuration file from the previous normal gem5 run.

Try:

> build/examples/{master,slave}_port/gem5.sc m5out/config.ini -e 1000000

It should run a simulation for 1us.

To see more information what happens inside the TLM modules use the -v flag:

> build/{master,slave}_port/gem5.sc m5out/config.ini -e 1000000 -v


V. Full System Setup
=====================

Apart from the simple examples, there is a full system example that uses
the gem5-to-TLM bridge.

Build gem5 as described in Section III. Then, make a config file for the
C++-configured gem5 using normal gem5

> ../../build/ARM/gem5.opt ../../configs/example/fs.py               \
  --tlm-memory=transactor --cpu-type=TimingSimpleCPU --num-cpu=1     \
  --mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \
  --l2cache --machine-type=VExpress_EMM                              \
  --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb        \
  --kernel=vmlinux.aarch32.ll_20131205.0-gem5                        \
  --disk-image=linux-aarch32-ael.img

The message "fatal: Can't find port handler type 'tlm_slave'" is okay.
The configuration will be stored in the m5out/ directory

The binary 'build/examples/slave_port/gem5.sc' can now be used to load in the
generated config file from the previous normal gem5 run.

Try:

> build/examples/slave_port/gem5.sc m5out/config.ini -o 2147483648

The parameter -o specifies the begining of the memory region (0x80000000).
The system should boot now.

For convenience a run_gem5_fs.sh file holds all those commands


VI. Elastic Trace Setup
========================

Elastic traces can also be replayed into the SystemC world.
For more information on elastic traces please refer to:

 - http://www.gem5.org/TraceCPU

 - Exploring System Performance using Elastic Traces:
   Fast, Accurate and Portable
   R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn.
   IEEE International Conference on Embedded Computer Systems Architectures
   Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece.

Similar to IV. the simulation can be set up with this command:

> ../../build/ARM/gem5.opt ./conf/tlm_elastic_slave.py

or

> ../../build/ARM/gem5.opt ./conf/tlm_elastic_slave_with_l2.py

Then:

> build/examples/slave_port/gem5.sc m5out/config.ini


VII. Knwon issues
=================

* For some toolchains, compiling libgem5 with tcmalloc leads to errors
  ('tcmalloc Attempt to free invalid pointer xxx') when linking libgem5 into a
  SystemC application.
* When SystemC is build with pthread support enabled, the binding of gem5 to
  SystemC breaks. When gem5 is linked to a SystemC application, gem5's usage
  of thread local storage results in a segfault.