README revision 11832
1955SN/AThis directory contains a demo of a coupling between gem5 and SystemC-TLM.  It
2955SN/Ais based on the gem5-systemc implementation in utils/systemc. This Readme gives
310841Sandreas.sandberg@arm.coman overall overview (I), describes the source files in this directory (II),
49812Sandreas.hansson@arm.comexplains the build steps (III), shows how to run example simulations (IV-VI)
59812Sandreas.hansson@arm.comand lists known issues (VII).
69812Sandreas.hansson@arm.com
79812Sandreas.hansson@arm.com
89812Sandreas.hansson@arm.comI. Overview
99812Sandreas.hansson@arm.com===========
109812Sandreas.hansson@arm.com
119812Sandreas.hansson@arm.comThe sources in this directory provide three SystemC modules that manage the
129812Sandreas.hansson@arm.comSystemC/gem5 co-simulation: Gem5SimControl, Gem5MasterTransactor, and
139812Sandreas.hansson@arm.comGem5SlaveTransactor. They also implement gem5's ExternalMaster::Port interface
149812Sandreas.hansson@arm.com(SCMasterPort) and ExternalSlave::Port interface (SCSlavePort).
157816Ssteve.reinhardt@amd.com
165871Snate@binkert.org**SCMasterPort** and **Gem5MasterTransactor** together form a TLM-to-gem5
171762SN/Abridge. SCMasterPort implements gem5's ExternalMaster::Port interface and forms
18955SN/Athe gem5 end of the bridge. Gem5MasterTransactor is a SystemC module that
19955SN/Aprovides a target socket and represents the TLM side of the bridge. All TLM
20955SN/Arequests send to this target socket, are translated to gem5 requests and
21955SN/Aforwarded to the gem5 world through the SCMasterPort. Then the gem5 world
22955SN/Ahandles the request and eventually issues a response. When the response arrives
23955SN/Aat the SCMasterPort it gets translated back into a TLM response and forwarded
24955SN/Ato the TLM world through target socket of the Gem5MasterTransactor.
25955SN/ASCMasterPort and Gem5MasterTransactor are bound to each other by configuring
26955SN/Athem for the same port name.
27955SN/A
28955SN/A**SCSlavePort** and **Gem5SlaveTransactor** together form a gem5-to-TLM bridge.
29955SN/AGem5SlaveTransactor is a SystemC module that provides a initiator socket and
30955SN/Arepresents the TLM end of the bridge. SCSlavePort implements gem5's
31955SN/AExternalSlave::Port interface and forms the gem5 side of the bridge. All gem5
32955SN/Arequests send to the SCSlavePort, are translated to TLM requests and forwarded
33955SN/Ato the TLM world through the initiator socket of the Gem5SlaveTransactor. Then
34955SN/Athe TLM world handles the request and eventually issues a response. When the
35955SN/Aresponse arrives at the Gem5SlaveTransactor it gets translated back into a TLM
36955SN/Aresponse and forwarded to the gem5 world through the SCSlavePort.  SCSLavePort
37955SN/Aand Gem5SlaveTransactor are bound to each other by configuring them for the
38955SN/Asame port name.
39955SN/A
40955SN/A**Gem5SimControl** is the central SystemC module that represents the complete
41955SN/Agem5 world. It is responsible for instantiating all gem5 objects according to a
422665Ssaidi@eecs.umich.edugiven configuration file, for configuring the simulation and for maintaining
432665Ssaidi@eecs.umich.eduthe gem5 event queue. It also keeps track of all SCMasterPort and SCSlavePort
445863Snate@binkert.organd responsible for connecting all Gem5MasterTransactor and Gem5SlaveTransactor
45955SN/Amodules to their gem5 counterparts. This module must be instantiated exactly
46955SN/Aonce in order to run a gem5 simulation from within an SystemC environment.
47955SN/A
48955SN/A
49955SN/AII. Files
508878Ssteve.reinhardt@amd.com=========
512632Sstever@eecs.umich.edu
528878Ssteve.reinhardt@amd.com    sc_slave_port.{cc,hh}     -- Implements SCSlavePort
532632Sstever@eecs.umich.edu    sc_master_port.{cc,hh}    -- Implements SCMasterPort
54955SN/A    sc_mm.{cc,hh}             -- Implementation of a TLM memory manager
558878Ssteve.reinhardt@amd.com    sc_ext.{cc,hh}            -- TLM extension that carries a gem5 packet
562632Sstever@eecs.umich.edu    sc_peq.{cc,hh}            -- TLM PEQ for scheduling gem5 events
572761Sstever@eecs.umich.edu    sim_control.{cc,hh}       -- Implements Gem5SimControl
582632Sstever@eecs.umich.edu    slave_transactor.{cc,hh}  -- Implements Gem5SlaveTransactor
592632Sstever@eecs.umich.edu    master_transactor.{cc,hh} -- Implements Gem5MasterTransactor
602632Sstever@eecs.umich.edu
612761Sstever@eecs.umich.edu    example/common/cli_parser.{cc,hh}     -- Simple cli argument parser
622761Sstever@eecs.umich.edu    example/common/report_hanlder.{cc,hh} -- Custom SystemC report handler
632761Sstever@eecs.umich.edu
648878Ssteve.reinhardt@amd.com    example/slave_port/main.cc           -- demonstration of the slave port
658878Ssteve.reinhardt@amd.com    example/slave_port/sc_target.{cc,hh} -- an example TLM LT/AT memory module
662761Sstever@eecs.umich.edu    example/slave_port/tlm.py            -- simple gem5 configuration
672761Sstever@eecs.umich.edu    example/slave_port/tlm_elastic.py    -- gem5 configuration with an elastic
682761Sstever@eecs.umich.edu                                            trace replayer
692761Sstever@eecs.umich.edu    example/slave_port/tgen.cfg          -- elastic traceplayer configuration
702761Sstever@eecs.umich.edu
718878Ssteve.reinhardt@amd.com    example/master_port/main.cc          -- demonstration of the master port
728878Ssteve.reinhardt@amd.com    example/master_port/traffic_generator.{cc/hh}
732632Sstever@eecs.umich.edu                                         -- an example traffic generator module
742632Sstever@eecs.umich.edu    example/master_port/tlm.py           -- simple gem5 configuration
758878Ssteve.reinhardt@amd.com
768878Ssteve.reinhardt@amd.comOther Files will be used from utils/systemc example:
772632Sstever@eecs.umich.edu
78955SN/A    sc_logger.{cc,hh},
79955SN/A    sc_module.{cc,hh},
80955SN/A    sc_gem5_control.{cc,hh},
815863Snate@binkert.org    stats.{cc,hh}
825863Snate@binkert.org
835863Snate@binkert.org
845863Snate@binkert.orgIII. Build
855863Snate@binkert.org==========
865863Snate@binkert.org
875863Snate@binkert.orgFirst build a normal gem5 (cxx-config not needed, Python needed).
885863Snate@binkert.orgSecond build gem5 as a library with cxx-config support and (optionally)
895863Snate@binkert.orgwithout python.
905863Snate@binkert.org
915863Snate@binkert.org> cd ../..
928878Ssteve.reinhardt@amd.com> scons build/ARM/gem5.opt
935863Snate@binkert.org> scons --with-cxx-config --without-python --without-tcmalloc \
945863Snate@binkert.org>       build/ARM/libgem5_opt.so
955863Snate@binkert.org> cd util/tlm
969812Sandreas.hansson@arm.com
979812Sandreas.hansson@arm.comNote: For MAC / OSX this command should be used:
985863Snate@binkert.org> scons --with-cxx-config --without-python --without-tcmalloc \
999812Sandreas.hansson@arm.com>       build/ARM/libgem5_opt.dylib
1005863Snate@binkert.org
1015863Snate@binkert.orgSet a proper LD_LIBRARY_PATH e.g. for bash:
1025863Snate@binkert.org> export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
1039812Sandreas.hansson@arm.com
1049812Sandreas.hansson@arm.comor for MAC / OSX:
1055863Snate@binkert.org> export DYLD_LIBRARY_PATH="$DYLD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
1065863Snate@binkert.org
1078878Ssteve.reinhardt@amd.comThe build system finds your SystemC installation using pkg-config. Make sure
1085863Snate@binkert.orgthat pkg-config is installed and your systemc.pc is within your
1095863Snate@binkert.orgPKG_CONFIG_PATH. You can add SystemC to the PKG_CONFIG_PATH using the following
1105863Snate@binkert.orgcommand:
1116654Snate@binkert.org> export PKG_CONFIG_PATH="/path/to/systemc/lib-<arch>/pkgconfig/:$PKG_CONFIG_PATH"
11210196SCurtis.Dunham@arm.com
113955SN/ATo build one of the examples:
1145396Ssaidi@eecs.umich.edu
11511401Sandreas.sandberg@arm.com> cd examples/{master,slave}_port
1165863Snate@binkert.org> scons
1175863Snate@binkert.org> cd ../../
1184202Sbinkertn@umich.edu
1195863Snate@binkert.org
1205863Snate@binkert.orgIV. Simple Examples
1215863Snate@binkert.org===================
1225863Snate@binkert.org
123955SN/A> cd examples/{master,slave}_port
1246654Snate@binkert.org
1255273Sstever@gmail.comIn order to run our example simulation, we first need to create a config.ini
1265871Snate@binkert.orgthat represents the gem5 configuration. We do so by starting gem5 with the
1275273Sstever@gmail.comdesired python configuration script.
1286655Snate@binkert.org
1298878Ssteve.reinhardt@amd.com> ../../../../build/ARM/gem5.opt ./tlm.py
1306655Snate@binkert.org
1316655Snate@binkert.orgThe message "fatal: Can't find port handler type 'tlm_{master,slave}'" is okay.
1329219Spower.jg@gmail.comThe configuration will be stored in the m5out/ directory
1336655Snate@binkert.org
1345871Snate@binkert.orgThe build step creates a binary gem5.opt.sc in the example directory.  It can
1356654Snate@binkert.orgnow be used to load in the generated configuration file from the previous
1368947Sandreas.hansson@arm.comnormal gem5 run.
1375396Ssaidi@eecs.umich.edu
1388120Sgblack@eecs.umich.eduTry:
1398120Sgblack@eecs.umich.edu
1408120Sgblack@eecs.umich.edu> ./gem5.opt.sc m5out/config.ini -e 1000000
1418120Sgblack@eecs.umich.edu
1428120Sgblack@eecs.umich.eduIt should run a simulation for 1us.
1438120Sgblack@eecs.umich.edu
1448120Sgblack@eecs.umich.eduTo see more information what happens inside the TLM modules use the -v flag:
1458120Sgblack@eecs.umich.edu
1468879Ssteve.reinhardt@amd.com> ./gem5.opt.sc m5out/config.ini -e 1000000 -v
1478879Ssteve.reinhardt@amd.com
1488879Ssteve.reinhardt@amd.comTo see more information about the port coupling use:
1498879Ssteve.reinhardt@amd.com
1508879Ssteve.reinhardt@amd.com> ./gem5.opt.sc m5out/config.ini -e 1000000 -d ExternalPort
1518879Ssteve.reinhardt@amd.com
1528879Ssteve.reinhardt@amd.com
1538879Ssteve.reinhardt@amd.comV. Full System Setup
1548879Ssteve.reinhardt@amd.com=====================
1558879Ssteve.reinhardt@amd.com
1568879Ssteve.reinhardt@amd.comApart from the simple examples, there is a full system example that uses
1578879Ssteve.reinhardt@amd.comthe gem5-to-TLM bridge.
1588879Ssteve.reinhardt@amd.com
1598120Sgblack@eecs.umich.edu>cd examples/slave_port
1608120Sgblack@eecs.umich.edu
1618120Sgblack@eecs.umich.eduBuild gem5 as described in Section III. Then, make a config file for the
1628120Sgblack@eecs.umich.eduC++-configured gem5 using normal gem5
1638120Sgblack@eecs.umich.edu
1648120Sgblack@eecs.umich.edu> ../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py   \
1658120Sgblack@eecs.umich.edu  --tlm-memory=transactor --cpu-type=timing --num-cpu=1              \
1668120Sgblack@eecs.umich.edu  --mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \
1678120Sgblack@eecs.umich.edu  --l2cache --machine-type=VExpress_EMM                              \
1688120Sgblack@eecs.umich.edu  --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb        \
1698120Sgblack@eecs.umich.edu  --kernel=vmlinux.aarch32.ll_20131205.0-gem5                        \
1708120Sgblack@eecs.umich.edu  --disk-image=linux-aarch32-ael.img
1718120Sgblack@eecs.umich.edu
1728120Sgblack@eecs.umich.eduThe message "fatal: Can't find port handler type 'tlm_slave'" is okay.
1738879Ssteve.reinhardt@amd.comThe configuration will be stored in the m5out/ directory
1748879Ssteve.reinhardt@amd.com
1758879Ssteve.reinhardt@amd.comThe binary 'gem5.opt.sc' can now be used to load in the generated config
1768879Ssteve.reinhardt@amd.comfile from the previous normal gem5 run.
17710458Sandreas.hansson@arm.com
17810458Sandreas.hansson@arm.comTry:
17910458Sandreas.hansson@arm.com
1808879Ssteve.reinhardt@amd.com> ./gem5.opt.sc m5out/config.ini -o 2147483648
1818879Ssteve.reinhardt@amd.com
1828879Ssteve.reinhardt@amd.comThe parameter -o specifies the begining of the memory region (0x80000000).
1838879Ssteve.reinhardt@amd.comThe system should boot now.
1849227Sandreas.hansson@arm.com
1859227Sandreas.hansson@arm.comFor convenience a run_gem5.sh file holds all those commands
1868879Ssteve.reinhardt@amd.com
1878879Ssteve.reinhardt@amd.com
1888879Ssteve.reinhardt@amd.comVI. Elastic Trace Setup
1898879Ssteve.reinhardt@amd.com========================
19010453SAndrew.Bardsley@arm.com
19110453SAndrew.Bardsley@arm.comElastic traces can also be replayed into the SystemC world.
19210453SAndrew.Bardsley@arm.comFor more information on elastic traces please refer to:
19310456SCurtis.Dunham@arm.com
19410456SCurtis.Dunham@arm.com - http://www.gem5.org/TraceCPU
19510456SCurtis.Dunham@arm.com
19610457Sandreas.hansson@arm.com - Exploring System Performance using Elastic Traces:
19710457Sandreas.hansson@arm.com   Fast, Accurate and Portable
19811342Sandreas.hansson@arm.com   R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn.
19911342Sandreas.hansson@arm.com   IEEE International Conference on Embedded Computer Systems Architectures
2008120Sgblack@eecs.umich.edu   Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece.
2018947Sandreas.hansson@arm.com
2027816Ssteve.reinhardt@amd.comSimilar IV. the simulation can be set up with this command:
2035871Snate@binkert.org
2045871Snate@binkert.org> ../../../../build/ARM/gem5.opt ./tlm_elastic.py
2056121Snate@binkert.org
2065871Snate@binkert.orgThen:
2075871Snate@binkert.org
2089926Sstan.czerniawski@arm.com> ./gem5.opt.sc m5out/config.ini
2099926Sstan.czerniawski@arm.com
2109119Sandreas.hansson@arm.com
21110068Sandreas.hansson@arm.comVII. Knwon issues
21210068Sandreas.hansson@arm.com=================
213955SN/A
2149416SAndreas.Sandberg@ARM.com* For some toolchains, compiling libgem5 with tcmalloc leads to errors
21511342Sandreas.hansson@arm.com  ('tcmalloc Attempt to free invalid pointer xxx') when linking libgem5 into a
21611212Sjoseph.gross@amd.com  SystemC application.
21711212Sjoseph.gross@amd.com* When SystemC was build with --enable-pthreads, SystemC applications linked
21811212Sjoseph.gross@amd.com