xref: /gem5/util/streamline/atomic_stat_config.ini

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# Author: Dam Sunwoo
#
# Sample stats config file (AtomicSimpleCPU) for m5stats2streamline.py
#
# Stats grouped together will show as grouped in Streamline.
# E.g.,
#
# commit_inst_count =
#     system.cpu#.commit.committedInsts
#     system.cpu#.commit.commitSquashedInsts
#
# will display the inst counts (committed/squashed) as a stacked line chart.
# Charts will still be configurable in Streamline.

[PER_CPU_STATS]
# '#' will be automatically replaced with the correct CPU id.

commit_inst_count =
    system.cpu#.committedInsts

cycles =
    system.cpu#.num_busy_cycles
    system.cpu#.num_idle_cycles

register_access =
    system.cpu#.num_int_register_reads
    system.cpu#.num_int_register_writes

mem_refs =
    system.cpu#.num_mem_refs

inst_breakdown =
    system.cpu#.num_conditional_control_insts
    system.cpu#.num_int_insts
    system.cpu#.num_fp_insts
    system.cpu#.num_load_insts
    system.cpu#.num_store_insts

icache =
    system.il1_cache#.overall_hits::total
    system.il1_cache#.overall_misses::total

dcache =
    system.dl1_cache#.overall_hits::total
    system.dl1_cache#.overall_misses::total

[PER_L2_STATS]
# '#' will be automatically replaced with the correct L2 id.

l2_cache =
    system.l2_cache#.overall_hits::total
    system.l2_cache#.overall_misses::total

[OTHER_STATS]
# Anything that doesn't belong to CPU or L2 caches

physmem =
    system.memsys.mem_ctrls.bytes_read::total
    system.memsys.mem_ctrls.bytes_written::total