m5op_x86.S revision 12464
17816Ssteve.reinhardt@amd.com/* 27816Ssteve.reinhardt@amd.com * Copyright (c) 2003-2006 The Regents of The University of Michigan 37816Ssteve.reinhardt@amd.com * All rights reserved. 47816Ssteve.reinhardt@amd.com * 57816Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 67816Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 77816Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 87816Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 97816Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 107816Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 117816Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 127816Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 137816Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 147816Ssteve.reinhardt@amd.com * this software without specific prior written permission. 157816Ssteve.reinhardt@amd.com * 167816Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177816Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187816Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197816Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207816Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217816Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227816Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237816Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247816Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257816Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267816Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277816Ssteve.reinhardt@amd.com * 287816Ssteve.reinhardt@amd.com * Authors: Gabe Black 2912563Sgabeblack@google.com * Nathan Binkert 3012563Sgabeblack@google.com * Ali Saidi 317816Ssteve.reinhardt@amd.com */ 327816Ssteve.reinhardt@amd.com 337816Ssteve.reinhardt@amd.com#include <gem5/asm/generic/m5ops.h> 347816Ssteve.reinhardt@amd.com 357816Ssteve.reinhardt@amd.com#if defined(M5OP_ADDR) && defined(M5OP_PIC) 367816Ssteve.reinhardt@amd.com/* Use the memory mapped m5op interface */ 377816Ssteve.reinhardt@amd.com#define TWO_BYTE_OP(name, number) \ 387816Ssteve.reinhardt@amd.com .globl name; \ 397816Ssteve.reinhardt@amd.com .func name; \ 407816Ssteve.reinhardt@amd.comname: \ 4112563Sgabeblack@google.com mov m5_mem@gotpcrel(%rip), %r11; \ 427816Ssteve.reinhardt@amd.com mov (%r11), %r11; \ 437816Ssteve.reinhardt@amd.com mov $number, %rax; \ 447816Ssteve.reinhardt@amd.com shl $8, %rax; \ 457816Ssteve.reinhardt@amd.com mov 0(%r11, %rax, 1), %rax; \ 467816Ssteve.reinhardt@amd.com ret; \ 477816Ssteve.reinhardt@amd.com .endfunc; 487816Ssteve.reinhardt@amd.com 497816Ssteve.reinhardt@amd.com#elif defined(M5OP_ADDR) && !defined(M5OP_PIC) 507816Ssteve.reinhardt@amd.com/* Use the memory mapped m5op interface */ 517816Ssteve.reinhardt@amd.com#define TWO_BYTE_OP(name, number) \ 527816Ssteve.reinhardt@amd.com .globl name; \ 537816Ssteve.reinhardt@amd.com .func name; \ 547816Ssteve.reinhardt@amd.comname: \ 557816Ssteve.reinhardt@amd.com mov m5_mem, %r11; \ 567816Ssteve.reinhardt@amd.com mov $number, %rax; \ 577816Ssteve.reinhardt@amd.com shl $8, %rax; \ 587816Ssteve.reinhardt@amd.com mov 0(%r11, %rax, 1), %rax; \ 597816Ssteve.reinhardt@amd.com ret; \ 607816Ssteve.reinhardt@amd.com .endfunc; 617816Ssteve.reinhardt@amd.com 627816Ssteve.reinhardt@amd.com#else 637816Ssteve.reinhardt@amd.com/* Use the magic instruction based m5op interface. This does not work 647816Ssteve.reinhardt@amd.com * in virtualized environments. 657816Ssteve.reinhardt@amd.com */ 6613709Sandreas.sandberg@arm.com 677816Ssteve.reinhardt@amd.com#define TWO_BYTE_OP(name, number) \ 687816Ssteve.reinhardt@amd.com .globl name; \ 697816Ssteve.reinhardt@amd.com .func name; \ 707816Ssteve.reinhardt@amd.comname: \ 717816Ssteve.reinhardt@amd.com .byte 0x0F, 0x04; \ 727816Ssteve.reinhardt@amd.com .word number; \ 737816Ssteve.reinhardt@amd.com ret; \ 747816Ssteve.reinhardt@amd.com .endfunc; 757816Ssteve.reinhardt@amd.com 767816Ssteve.reinhardt@amd.com#endif 777816Ssteve.reinhardt@amd.com 787816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_arm, M5OP_ARM) 797816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_quiesce, M5OP_QUIESCE) 807816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_quiesce_ns, M5OP_QUIESCE_NS) 817816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_quiesce_cycle, M5OP_QUIESCE_CYCLE) 827816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_quiesce_time, M5OP_QUIESCE_TIME) 837816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_rpns, M5OP_RPNS) 847816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_wake_cpu, M5OP_WAKE_CPU) 857816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_exit, M5OP_EXIT) 867816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_fail, M5OP_FAIL) 8713709Sandreas.sandberg@arm.comTWO_BYTE_OP(m5_init_param, M5OP_INIT_PARAM) 887816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_load_symbol, M5OP_LOAD_SYMBOL) 897816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_reset_stats, M5OP_RESET_STATS) 907816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_dump_stats, M5OP_DUMP_STATS) 917816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_dump_reset_stats, M5OP_DUMP_RESET_STATS) 927816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_checkpoint, M5OP_CHECKPOINT) 937816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_read_file, M5OP_READ_FILE) 947816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_write_file, M5OP_WRITE_FILE) 957816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_debug_break, M5OP_DEBUG_BREAK) 967816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_switch_cpu, M5OP_SWITCH_CPU) 977816Ssteve.reinhardt@amd.comTWO_BYTE_OP(m5_add_symbol, M5OP_ADD_SYMBOL) 988947Sandreas.hansson@arm.comTWO_BYTE_OP(m5_panic, M5OP_PANIC) 998947Sandreas.hansson@arm.comTWO_BYTE_OP(m5_work_begin, M5OP_WORK_BEGIN) 1008947Sandreas.hansson@arm.comTWO_BYTE_OP(m5_work_end, M5OP_WORK_END) 1018947Sandreas.hansson@arm.comTWO_BYTE_OP(m5_dist_toggle_sync, M5OP_DIST_TOGGLE_SYNC) 1028947Sandreas.hansson@arm.com