m5op_arm.S revision 8987:a5add07e066c
17732SAli.Saidi@ARM.com/* 27732SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37732SAli.Saidi@ARM.com * All rights reserved 47732SAli.Saidi@ARM.com * 57732SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67732SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77732SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87732SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97732SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107732SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117732SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127732SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137732SAli.Saidi@ARM.com * 147732SAli.Saidi@ARM.com * Copyright (c) 2003-2006 The Regents of The University of Michigan 157732SAli.Saidi@ARM.com * All rights reserved. 167732SAli.Saidi@ARM.com * 177732SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 187732SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 197732SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 207732SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 217732SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 227732SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 237732SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 247732SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 257732SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 267732SAli.Saidi@ARM.com * this software without specific prior written permission. 277732SAli.Saidi@ARM.com * 287732SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297732SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307732SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317732SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327732SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337732SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347732SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357732SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367732SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377732SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387732SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397732SAli.Saidi@ARM.com * 407732SAli.Saidi@ARM.com * Authors: Nathan Binkert 417732SAli.Saidi@ARM.com * Ali Saidi 427732SAli.Saidi@ARM.com * Chander Sudanthi 439660SAndreas.Sandberg@ARM.com */ 447732SAli.Saidi@ARM.com.syntax unified 458987SAli.Saidi@ARM.com#ifdef __thumb__ 468987SAli.Saidi@ARM.com.thumb 478987SAli.Saidi@ARM.com#endif 488987SAli.Saidi@ARM.com 497732SAli.Saidi@ARM.com#define m5_op 0xEE 507732SAli.Saidi@ARM.com 517732SAli.Saidi@ARM.com#include "m5ops.h" 527732SAli.Saidi@ARM.com 537732SAli.Saidi@ARM.com#ifdef __thumb__ 549660SAndreas.Sandberg@ARM.com#define INST(op, ra, rb, func) \ 559686Sandreas@sandberg.pp.se .short (((op) << 8) | (func)); \ 569660SAndreas.Sandberg@ARM.com .short (((ra) << 12) | (0x1 << 8) | (0x1 << 4) | (rb)) 579660SAndreas.Sandberg@ARM.com/* m5ops m5func */ 589660SAndreas.Sandberg@ARM.com/* ra coproc 1 op=1 rb */ 599660SAndreas.Sandberg@ARM.com#else 609660SAndreas.Sandberg@ARM.com#define INST(op, ra, rb, func) \ 619660SAndreas.Sandberg@ARM.com .long (((op) << 24) | ((func) << 16) | ((ra) << 12) | (0x1 << 8) | (0x1 << 4) | (rb)) 629660SAndreas.Sandberg@ARM.com/* m5ops m5func ra coproc 1 op=1 rb */ 639686Sandreas@sandberg.pp.se#endif 649686Sandreas@sandberg.pp.se 659686Sandreas@sandberg.pp.se#define LEAF(func) \ 669686Sandreas@sandberg.pp.se .globl func; \ 679686Sandreas@sandberg.pp.sefunc: 689660SAndreas.Sandberg@ARM.com 699660SAndreas.Sandberg@ARM.com#define RET \ 709660SAndreas.Sandberg@ARM.com mov pc,lr 717732SAli.Saidi@ARM.com 729660SAndreas.Sandberg@ARM.com#define END(func) \ 739660SAndreas.Sandberg@ARM.com 749660SAndreas.Sandberg@ARM.com#define SIMPLE_OP(_f, _o) \ 759660SAndreas.Sandberg@ARM.com LEAF(_f) \ 769660SAndreas.Sandberg@ARM.com _o; \ 779660SAndreas.Sandberg@ARM.com RET; \ 789686Sandreas@sandberg.pp.se END(_f) 799660SAndreas.Sandberg@ARM.com 809660SAndreas.Sandberg@ARM.com#define ARM INST(m5_op, 0, 0, arm_func) 819660SAndreas.Sandberg@ARM.com#define QUIESCE INST(m5_op, 0, 0, quiesce_func) 827732SAli.Saidi@ARM.com#define QUIESCENS INST(m5_op, 0, 0, quiescens_func) 839660SAndreas.Sandberg@ARM.com#define QUIESCECYC INST(m5_op, 0, 0, quiescecycle_func) 849660SAndreas.Sandberg@ARM.com#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func) 859660SAndreas.Sandberg@ARM.com#define RPNS INST(m5_op, 0, 0, rpns_func) 869660SAndreas.Sandberg@ARM.com#define WAKE_CPU INST(m5_op, 0, 0, wakecpu_func) 879660SAndreas.Sandberg@ARM.com#define M5EXIT INST(m5_op, 0, 0, exit_func) 889660SAndreas.Sandberg@ARM.com#define INITPARAM INST(m5_op, 0, 0, initparam_func) 899660SAndreas.Sandberg@ARM.com#define LOADSYMBOL INST(m5_op, 0, 0, loadsymbol_func) 909660SAndreas.Sandberg@ARM.com#define RESET_STATS INST(m5_op, 0, 0, resetstats_func) 919660SAndreas.Sandberg@ARM.com#define DUMP_STATS INST(m5_op, 0, 0, dumpstats_func) 929660SAndreas.Sandberg@ARM.com#define DUMPRST_STATS INST(m5_op, 0, 0, dumprststats_func) 939660SAndreas.Sandberg@ARM.com#define CHECKPOINT INST(m5_op, 0, 0, ckpt_func) 949660SAndreas.Sandberg@ARM.com#define READFILE INST(m5_op, 0, 0, readfile_func) 959660SAndreas.Sandberg@ARM.com#define WRITEFILE INST(m5_op, 0, 0, writefile_func) 969660SAndreas.Sandberg@ARM.com#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func) 979660SAndreas.Sandberg@ARM.com#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func) 989660SAndreas.Sandberg@ARM.com#define ADDSYMBOL INST(m5_op, 0, 0, addsymbol_func) 999660SAndreas.Sandberg@ARM.com#define PANIC INST(m5_op, 0, 0, panic_func) 1009660SAndreas.Sandberg@ARM.com#define WORK_BEGIN INST(m5_op, 0, 0, work_begin_func) 1019660SAndreas.Sandberg@ARM.com#define WORK_END INST(m5_op, 0, 0, work_end_func) 1029660SAndreas.Sandberg@ARM.com 1039660SAndreas.Sandberg@ARM.com#define AN_BSM INST(m5_op, an_bsm, 0, annotate_func) 1049660SAndreas.Sandberg@ARM.com#define AN_ESM INST(m5_op, an_esm, 0, annotate_func) 1059660SAndreas.Sandberg@ARM.com#define AN_BEGIN INST(m5_op, an_begin, 0, annotate_func) 1069660SAndreas.Sandberg@ARM.com#define AN_END INST(m5_op, an_end, 0, annotate_func) 1079660SAndreas.Sandberg@ARM.com#define AN_Q INST(m5_op, an_q, 0, annotate_func) 1089660SAndreas.Sandberg@ARM.com#define AN_RQ INST(m5_op, an_rq, 0, annotate_func) 1099660SAndreas.Sandberg@ARM.com#define AN_DQ INST(m5_op, an_dq, 0, annotate_func) 1109660SAndreas.Sandberg@ARM.com#define AN_WF INST(m5_op, an_wf, 0, annotate_func) 1119660SAndreas.Sandberg@ARM.com#define AN_WE INST(m5_op, an_we, 0, annotate_func) 1129660SAndreas.Sandberg@ARM.com#define AN_WS INST(m5_op, an_ws, 0, annotate_func) 1139660SAndreas.Sandberg@ARM.com#define AN_SQ INST(m5_op, an_sq, 0, annotate_func) 1149660SAndreas.Sandberg@ARM.com#define AN_AQ INST(m5_op, an_aq, 0, annotate_func) 1159660SAndreas.Sandberg@ARM.com#define AN_PQ INST(m5_op, an_pq, 0, annotate_func) 1169660SAndreas.Sandberg@ARM.com#define AN_L INST(m5_op, an_l, 0, annotate_func) 1179660SAndreas.Sandberg@ARM.com#define AN_IDENTIFY INST(m5_op, an_identify, 0, annotate_func) 1189660SAndreas.Sandberg@ARM.com#define AN_GETID INST(m5_op, an_getid, 0, annotate_func) 1199660SAndreas.Sandberg@ARM.com 1209660SAndreas.Sandberg@ARM.com.text 1219660SAndreas.Sandberg@ARM.com 1229660SAndreas.Sandberg@ARM.comSIMPLE_OP(arm, ARM) 1239660SAndreas.Sandberg@ARM.comSIMPLE_OP(quiesce, QUIESCE) 124SIMPLE_OP(quiesceNs, QUIESCENS) 125SIMPLE_OP(quiesceCycle, QUIESCECYC) 126SIMPLE_OP(quiesceTime, QUIESCETIME) 127SIMPLE_OP(rpns, RPNS) 128SIMPLE_OP(wakeCPU, WAKE_CPU) 129SIMPLE_OP(m5_exit, M5EXIT) 130SIMPLE_OP(m5_initparam, INITPARAM) 131SIMPLE_OP(m5_loadsymbol, LOADSYMBOL) 132SIMPLE_OP(m5_reset_stats, RESET_STATS) 133SIMPLE_OP(m5_dump_stats, DUMP_STATS) 134SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS) 135SIMPLE_OP(m5_checkpoint, CHECKPOINT) 136SIMPLE_OP(m5_readfile, READFILE) 137SIMPLE_OP(m5_writefile, WRITEFILE) 138SIMPLE_OP(m5_debugbreak, DEBUGBREAK) 139SIMPLE_OP(m5_switchcpu, SWITCHCPU) 140SIMPLE_OP(m5_addsymbol, ADDSYMBOL) 141SIMPLE_OP(m5_panic, PANIC) 142SIMPLE_OP(m5_work_begin, WORK_BEGIN) 143SIMPLE_OP(m5_work_end, WORK_END) 144 145SIMPLE_OP(m5a_bsm, AN_BSM) 146SIMPLE_OP(m5a_esm, AN_ESM) 147SIMPLE_OP(m5a_begin, AN_BEGIN) 148SIMPLE_OP(m5a_end, AN_END) 149SIMPLE_OP(m5a_q, AN_Q) 150SIMPLE_OP(m5a_rq, AN_RQ) 151SIMPLE_OP(m5a_dq, AN_DQ) 152SIMPLE_OP(m5a_wf, AN_WF) 153SIMPLE_OP(m5a_we, AN_WE) 154SIMPLE_OP(m5a_ws, AN_WS) 155SIMPLE_OP(m5a_sq, AN_SQ) 156SIMPLE_OP(m5a_aq, AN_AQ) 157SIMPLE_OP(m5a_pq, AN_PQ) 158SIMPLE_OP(m5a_l, AN_L) 159SIMPLE_OP(m5a_identify, AN_IDENTIFY) 160SIMPLE_OP(m5a_getid, AN_GETID) 161 162