m5op_arm.S revision 9686 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Nathan Binkert
41 *          Ali Saidi
42 *          Chander Sudanthi
43 *          Andreas Sandberg
44 */
45.syntax unified
46#ifdef __thumb__
47.thumb
48#endif
49
50#include "m5ops.h"
51
52.text
53
54.macro simple_op name, func, subfunc
55        .align 2
56        .globl \name
57\name:
58        /* First, try to trap into m5 using the m5-kvm hypercall
59         * hack. The bxj will become a branch to the fallback code
60         * if it is executed in the normal m5 environment.
61         */
62        push {lr}
63#ifdef __thumb__
64        adr lr, 1f+1
65#else
66        adr lr, 1f
67#endif
68        ldr ip, =((((\func) & 0xFF) << 8) | ((\subfunc) & 0xFF))
69        bxj lr
70        pop {pc}
71
72        /* Old-style m5 pseudo instruction using CP1 accesses */
731:
74#ifdef __thumb__
75        .short 0xEE00 | \func
76        .short 0x0110 | (\subfunc << 12)
77#else
78        .long (0xEE000110 | (\func << 16) | (\subfunc << 12))
79#endif
80        pop {pc}
81.endm
82
83#define SIMPLE_OP(name, func, subfunc) simple_op name, func, subfunc
84
85SIMPLE_OP(arm, arm_func, 0)
86SIMPLE_OP(quiesce, quiesce_func, 0)
87SIMPLE_OP(quiesceNs, quiescens_func, 0)
88SIMPLE_OP(quiesceCycle, quiescecycle_func, 0)
89SIMPLE_OP(quiesceTime, quiescetime_func, 0)
90SIMPLE_OP(rpns, rpns_func, 0)
91SIMPLE_OP(wakeCPU, wakecpu_func, 0)
92SIMPLE_OP(m5_exit, exit_func, 0)
93SIMPLE_OP(m5_initparam, initparam_func, 0)
94SIMPLE_OP(m5_loadsymbol, loadsymbol_func, 0)
95SIMPLE_OP(m5_reset_stats, resetstats_func, 0)
96SIMPLE_OP(m5_dump_stats, dumpstats_func, 0)
97SIMPLE_OP(m5_dumpreset_stats, dumprststats_func, 0)
98SIMPLE_OP(m5_checkpoint, ckpt_func, 0)
99SIMPLE_OP(m5_readfile, readfile_func, 0)
100SIMPLE_OP(m5_writefile, writefile_func, 0)
101SIMPLE_OP(m5_debugbreak, debugbreak_func, 0)
102SIMPLE_OP(m5_switchcpu, switchcpu_func, 0)
103SIMPLE_OP(m5_addsymbol, addsymbol_func, 0)
104SIMPLE_OP(m5_panic, panic_func, 0)
105SIMPLE_OP(m5_work_begin, work_begin_func, 0)
106SIMPLE_OP(m5_work_end, work_end_func, 0)
107
108SIMPLE_OP(m5a_bsm, annotate_func, an_bsm)
109SIMPLE_OP(m5a_esm, annotate_func, an_esm)
110SIMPLE_OP(m5a_begin, annotate_func, an_begin)
111SIMPLE_OP(m5a_end, annotate_func, an_end)
112SIMPLE_OP(m5a_q, annotate_func, an_q)
113SIMPLE_OP(m5a_rq, annotate_func, an_rq)
114SIMPLE_OP(m5a_dq, annotate_func, an_dq)
115SIMPLE_OP(m5a_wf, annotate_func, an_wf)
116SIMPLE_OP(m5a_we, annotate_func, an_we)
117SIMPLE_OP(m5a_ws, annotate_func, an_ws)
118SIMPLE_OP(m5a_sq, annotate_func, an_sq)
119SIMPLE_OP(m5a_aq, annotate_func, an_aq)
120SIMPLE_OP(m5a_pq, annotate_func, an_pq)
121SIMPLE_OP(m5a_l, annotate_func, an_l)
122SIMPLE_OP(m5a_identify, annotate_func, an_identify)
123SIMPLE_OP(m5a_getid, annotate_func, an_getid)
124