m5op_alpha.S revision 3089
1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Ali Saidi 30 */ 31 32#define m5_op 0x01 33 34#define arm_func 0x00 35#define quiesce_func 0x01 36#define quiescens_func 0x02 37#define quiescecycle_func 0x03 38#define quiescetime_func 0x04 39#define ivlb_func 0x10 40#define ivle_func 0x11 41#define exit_old_func 0x20 // deprectated! 42#define exit_func 0x21 43#define initparam_func 0x30 44#define resetstats_func 0x40 45#define dumpstats_func 0x41 46#define dumprststats_func 0x42 47#define ckpt_func 0x43 48#define readfile_func 0x50 49#define debugbreak_func 0x51 50#define switchcpu_func 0x52 51#define addsymbol_func 0x53 52#define panic_func 0x54 53#define anbegin_func 0x55 54#define anwait_func 0x56 55 56#define INST(op, ra, rb, func) \ 57 .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) 58 59#define LEAF(func) \ 60 .align 3; \ 61 .globl func; \ 62 .ent func; \ 63func: 64 65#define RET \ 66 ret ($26) 67 68#define END(func) \ 69 .end func 70 71#define ARM(reg) INST(m5_op, reg, 0, arm_func) 72#define QUIESCE INST(m5_op, 0, 0, quiesce_func) 73#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func) 74#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func) 75#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func) 76#define IVLB(reg) INST(m5_op, reg, 0, ivlb_func) 77#define IVLE(reg) INST(m5_op, reg, 0, ivle_func) 78#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func) 79#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func) 80#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func) 81#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func) 82#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func) 83#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func) 84#define READFILE INST(m5_op, 0, 0, readfile_func) 85#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func) 86#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func) 87#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func) 88#define PANIC INST(m5_op, 0, 0, panic_func) 89#define AN_BEGIN(r1) INST(m5_op, r1, 0, anbegin_func) 90#define AN_WAIT(r1,r2) INST(m5_op, r1, r2, anwait_func) 91 92 .set noreorder 93 94 .align 4 95LEAF(arm) 96 ARM(16) 97 RET 98END(arm) 99 100 .align 4 101LEAF(quiesce) 102 QUIESCE 103 RET 104END(quiesce) 105 106 .align 4 107LEAF(quiesceNs) 108 QUIESCENS(16) 109 RET 110END(quiesceNs) 111 112 .align 4 113LEAF(quiesceCycle) 114 QUIESCECYC(16) 115 RET 116END(quiesceCycle) 117 118 .align 4 119LEAF(quiesceTime) 120 QUIESCETIME 121 RET 122END(quiesceTime) 123 124 125 .align 4 126LEAF(m5_ivlb) 127 IVLB(16) 128 RET 129END(m5_ivlb) 130 131 .align 4 132LEAF(m5_ivle) 133 IVLE(16) 134 RET 135END(m5_ivle) 136 137 .align 4 138LEAF(m5_exit) 139 M5EXIT(16) 140 RET 141END(m5_exit) 142 143 .align 4 144LEAF(m5_initparam) 145 INITPARAM(0) 146 RET 147END(m5_initparam) 148 149 .align 4 150LEAF(m5_reset_stats) 151 RESET_STATS(16, 17) 152 RET 153END(m5_reset_stats) 154 155 .align 4 156LEAF(m5_dump_stats) 157 DUMP_STATS(16, 17) 158 RET 159END(m5_dump_stats) 160 161 .align 4 162LEAF(m5_dumpreset_stats) 163 DUMPRST_STATS(16, 17) 164 RET 165END(m5_dumpreset_stats) 166 167 .align 4 168LEAF(m5_checkpoint) 169 CHECKPOINT(16, 17) 170 RET 171END(m5_checkpoint) 172 173 .align 4 174LEAF(m5_readfile) 175 READFILE 176 RET 177END(m5_readfile) 178 179 .align 4 180LEAF(m5_debugbreak) 181 DEBUGBREAK 182 RET 183END(m5_debugbreak) 184 185 .align 4 186LEAF(m5_switchcpu) 187 SWITCHCPU 188 RET 189END(m5_switchcpu) 190 191 .align 4 192LEAF(m5_addsymbol) 193 ADDSYMBOL(16, 17) 194 RET 195END(m5_addsymbol) 196 197 .align 4 198LEAF(m5_panic) 199 PANIC 200 RET 201END(m5_panic) 202 203 204 .align 4 205LEAF(m5_anbegin) 206 AN_BEGIN(16) 207 RET 208END(m5_anbegin) 209 210 211 .align 4 212LEAF(m5_anwait) 213 AN_WAIT(16,17) 214 RET 215END(m5_anwait) 216 217 218